| #
4a871b56 |
| 21-Mar-2025 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge changes from topic "ar/cvereorder" into integration
* changes:
chore(cpus): rearrange the errata and cve order in Neoverse-N2
chore(cpus): rearrange cve in order in Cortex-X1
chore(cpus)
Merge changes from topic "ar/cvereorder" into integration
* changes:
chore(cpus): rearrange the errata and cve order in Neoverse-N2
chore(cpus): rearrange cve in order in Cortex-X1
chore(cpus): fix cve order in Neoverse-V1
chore(cpus): fix cve order in Cortex-X2
chore(cpus): fix cve order in Cortex-A78C
chore(cpus): fix cve order in Cortex-A78_AE
chore(cpus): fix cve order in Cortex-A78
chore(cpus): fix cve order in Cortex-A77
show more ...
|
| #
e83cccfe |
| 17-Mar-2025 |
Sona Mathew <sonarebecca.mathew@arm.com> |
chore(cpus): rearrange cve in order in Cortex-X1
Patch rearranges CVE-2024-5660 in ascending order based on
the year and index for Cortex X1.
Change-Id: I0c4206e38f09b1f88ee95e8ce69d7e13b8a9bb2d
Si
chore(cpus): rearrange cve in order in Cortex-X1
Patch rearranges CVE-2024-5660 in ascending order based on
the year and index for Cortex X1.
Change-Id: I0c4206e38f09b1f88ee95e8ce69d7e13b8a9bb2d
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
show more ...
|
| #
a8a5d39d |
| 24-Feb-2025 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes from topic "bk/errata_speed" into integration
* changes:
refactor(cpus): declare runtime errata correctly
perf(cpus): make reset errata do fewer branches
perf(cpus): inline the i
Merge changes from topic "bk/errata_speed" into integration
* changes:
refactor(cpus): declare runtime errata correctly
perf(cpus): make reset errata do fewer branches
perf(cpus): inline the init_cpu_data_ptr function
perf(cpus): inline the reset function
perf(cpus): inline the cpu_get_rev_var call
perf(cpus): inline cpu_rev_var checks
refactor(cpus): register DSU errata with the errata framework's wrappers
refactor(cpus): convert checker functions to standard helpers
refactor(cpus): convert the Cortex-A65 to use the errata framework
fix(cpus): declare reset errata correctly
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|
| #
89dba82d |
| 22-Jan-2025 |
Boyan Karatotev <boyan.karatotev@arm.com> |
perf(cpus): make reset errata do fewer branches
Errata application is painful for performance. For a start, it's done
when the core has just come out of reset, which means branch predictors
and cach
perf(cpus): make reset errata do fewer branches
Errata application is painful for performance. For a start, it's done
when the core has just come out of reset, which means branch predictors
and caches will be empty so a branch to a workaround function must be
fetched from memory and that round trip is very slow. Then it also runs
with the I-cache off, which means that the loop to iterate over the
workarounds must also be fetched from memory on each iteration.
We can remove both branches. First, we can simply apply every erratum
directly instead of defining a workaround function and jumping to it.
Currently, no errata that need to be applied at both reset and runtime,
with the same workaround function, exist. If the need arose in future,
this should be achievable with a reset + runtime wrapper combo.
Then, we can construct a function that applies each erratum linearly
instead of looping over the list. If this function is part of the reset
function, then the only "far" branches at reset will be for the checker
functions. Importantly, this mitigates the slowdown even when an erratum
is disabled.
The result is ~50% speedup on N1SDP and ~20% on AArch64 Juno on wakeup
from PSCI calls that end in powerdown. This is roughly back to the
baseline of v2.9, before the errata framework regressed on performance
(or a little better). It is important to note that there are other
slowdowns since then that remain unknown.
Change-Id: Ie4d5288a331b11fd648e5c4a0b652b74160b07b9
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
show more ...
|
| #
08bbe245 |
| 18-Dec-2024 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge changes from topic "sm/fix_erratum" into integration
* changes:
fix(cpus): workaround for CVE-2024-5660 for Cortex-X925
fix(cpus): workaround for CVE-2024-5660 for Cortex-X2
fix(cpus): w
Merge changes from topic "sm/fix_erratum" into integration
* changes:
fix(cpus): workaround for CVE-2024-5660 for Cortex-X925
fix(cpus): workaround for CVE-2024-5660 for Cortex-X2
fix(cpus): workaround for CVE-2024-5660 for Cortex-A77
fix(cpus): workaround for CVE-2024-5660 for Neoverse-V1
fix(cpus): workaround for CVE-2024-5660 for Cortex-A78_AE
fix(cpus): workaround for CVE-2024-5660 for Cortex-A78C
fix(cpus): workaround for CVE-2024-5660 for Cortex-A78
fix(cpus): workaround for CVE-2024-5660 for Cortex-X1
fix(cpus): workaround for CVE-2024-5660 for Neoverse-N2
fix(cpus): workaround for CVE-2024-5660 for Cortex-A710
fix(cpus): workaround for CVE-2024-5660 for Neoverse-V2
fix(cpus): workaround for CVE-2024-5660 for Cortex-X3
fix(cpus): workaround for CVE-2024-5660 for Neoverse-V3
fix(cpus): workaround for CVE-2024-5660 for Cortex-X4
show more ...
|
| #
26293a74 |
| 23-May-2024 |
Sona Mathew <sonarebecca.mathew@arm.com> |
fix(cpus): workaround for CVE-2024-5660 for Cortex-X1
Implements mitigation for CVE-2024-5660 that affects Cortex-X1
revisions r0p0, r1p0, r1p1, r1p2.
The workaround is to disable the hardware page
fix(cpus): workaround for CVE-2024-5660 for Cortex-X1
Implements mitigation for CVE-2024-5660 that affects Cortex-X1
revisions r0p0, r1p0, r1p1, r1p2.
The workaround is to disable the hardware page aggregation at
EL3 by setting CPUECTLR_EL1[46] = 1'b1.
Public Documentation:
https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-5660
Change-Id: I3124db3980f2786412369a010ca6abbbbaa3b601
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
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|
| #
cc4f3838 |
| 27-Aug-2024 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes from topic "clean-up-errata-compatibility" into integration
* changes:
refactor(cpus): remove cpu specific errata funcs
refactor(cpus): directly invoke errata reporter
|
| #
3fb52e41 |
| 14-May-2024 |
Ryan Everett <ryan.everett@arm.com> |
refactor(cpus): remove cpu specific errata funcs
Errata printing is done directly via generic_errata_report.
This commit removes the unused \_cpu\()_errata_report
functions for all cores, and remove
refactor(cpus): remove cpu specific errata funcs
Errata printing is done directly via generic_errata_report.
This commit removes the unused \_cpu\()_errata_report
functions for all cores, and removes errata_func from cpu_ops.
Change-Id: I04fefbde5f0ff63b1f1cd17c864557a14070d68c
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
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|
| #
fc22bcf8 |
| 03-Aug-2023 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge changes from topic "gr/errata_refactor" into integration
* changes:
refactor(cpus): convert the Cortex-A55 to use cpu helpers
refactor(cpus): convert the Cortex-A55 to use the errata frame
Merge changes from topic "gr/errata_refactor" into integration
* changes:
refactor(cpus): convert the Cortex-A55 to use cpu helpers
refactor(cpus): convert the Cortex-A55 to use the errata framework
refactor(cpus): convert the Cortex-A76AE to use cpu helpers
refactor(cpus): convert the Cortex-A76AE to use the errata framework
refactor(cpus): convert the Cortex-A78 to use cpu helpers
refactor(cpus): convert the Cortex-A78 to use the errata framework
refactor(cpus): reorder Cortex-A78 errata by ascending order
refactor(cpus): convert the Cortex-A78C to use cpu helpers
refactor(cpus): convert the Cortex-A78C to use the errata framework
refactor(cpus): reorder Cortex-A78C errata by ascending order
refactor(cpus): convert the Cortex-X1 to use cpu helpers
refactor(cpus): convert the Cortex-X1 to use the errata framework
refactor(cpus): reorder Cortex-X1 errata by ascending order
refactor(cpus): use cpu errata wrappers Cortex-A12 aarch32 cpu
refactor(cpus): use cpu errata wrappers Cortex-A7 and A9 aarch32 cpus
show more ...
|
| #
1ff96d6d |
| 15-Jun-2023 |
Govindraj Raja <govindraj.raja@arm.com> |
refactor(cpus): convert the Cortex-X1 to use cpu helpers
Change-Id: I0b62fa613eab4a7545408c0da0c05f88f5f28838
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
|
| #
21106868 |
| 15-Jun-2023 |
Govindraj Raja <govindraj.raja@arm.com> |
refactor(cpus): convert the Cortex-X1 to use the errata framework
Testing:
- Manual comparison of disassembly with and without conversion.
- Using the test script in gerrit - 19136
- Building
refactor(cpus): convert the Cortex-X1 to use the errata framework
Testing:
- Manual comparison of disassembly with and without conversion.
- Using the test script in gerrit - 19136
- Building with errata and stepping through from ArmDS and running tftf.
Change-Id: Ie3909ef51c28a24728752a08ddf96a48d87d3cd7
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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|
| #
e76cfe50 |
| 15-Jun-2023 |
Govindraj Raja <govindraj.raja@arm.com> |
refactor(cpus): reorder Cortex-X1 errata by ascending order
Change-Id: I1e580dd330b545370b23d4b9704d899f6a679250
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
|
| #
fecd243c |
| 02-May-2023 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "refactor(cpus): use BIT macro in a consistent manner" into integration
|
| #
baeaf292 |
| 28-Apr-2023 |
Okash Khawaja <okash@google.com> |
refactor(cpus): use BIT macro in a consistent manner
In assembly code, BIT macro is used with a preceding hash #. Let's
update Cortex X1 code to follow the same convention. Excluding hash
doesn't ca
refactor(cpus): use BIT macro in a consistent manner
In assembly code, BIT macro is used with a preceding hash #. Let's
update Cortex X1 code to follow the same convention. Excluding hash
doesn't cause compilation to fail or emit incorrect code.
Signed-off-by: Okash Khawaja <okash@google.com>
Change-Id: If304cdf90542d2edcab3e2d66cd7e905ff7fd047
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|
| #
401cb4bb |
| 11-May-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "fix(security): workaround for CVE-2022-23960 for Cortex-X1" into integration
|
| #
c8c7c47b |
| 11-May-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "fix(errata): workarounds for cortex-x1 errata" into integration
|
| #
123cebe5 |
| 11-May-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "feat(cpu): add support for Cortex-X1" into integration
|
| #
e81e999b |
| 21-Apr-2022 |
Okash Khawaja <okash@google.com> |
fix(security): workaround for CVE-2022-23960 for Cortex-X1
Implements the loop workaround for Cortex-X1.
Signed-off-by: Okash Khawaja <okash@google.com>
Change-Id: I5828a26c1ec3cfb718246ea5c3b099da
fix(security): workaround for CVE-2022-23960 for Cortex-X1
Implements the loop workaround for Cortex-X1.
Signed-off-by: Okash Khawaja <okash@google.com>
Change-Id: I5828a26c1ec3cfb718246ea5c3b099dabc0fb3d7
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|
| #
7b76c20d |
| 21-Apr-2022 |
Okash Khawaja <okash@google.com> |
fix(errata): workarounds for cortex-x1 errata
This patch adds workarounds for following cortex-x1 errata:
- 1821534 (CatB)
- 1688305 (CatB)
- 1827429 (CatB)
SDEN can be found here:
https://develop
fix(errata): workarounds for cortex-x1 errata
This patch adds workarounds for following cortex-x1 errata:
- 1821534 (CatB)
- 1688305 (CatB)
- 1827429 (CatB)
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401782/latest
Signed-off-by: Okash Khawaja <okash@google.com>
Change-Id: I10ebe8d5c56a6d273820bb2c682f21bf98daa7a5
show more ...
|
| #
6e8eca78 |
| 21-Apr-2022 |
Okash Khawaja <okash@google.com> |
feat(cpu): add support for Cortex-X1
This patch adds basic CPU library code to support Cortex-X1 CPU in TF-A.
Follow-up patches will add selected errata workarounds for this CPU.
Signed-off-by: Oka
feat(cpu): add support for Cortex-X1
This patch adds basic CPU library code to support Cortex-X1 CPU in TF-A.
Follow-up patches will add selected errata workarounds for this CPU.
Signed-off-by: Okash Khawaja <okash@google.com>
Change-Id: I4a3d50a98bf55a555bfaefeed5c7b88a35e3bc21
show more ...
|