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Searched refs:ret (Results 1 – 25 of 737) sorted by relevance

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/rk3399_ARM-atf/drivers/nxp/clk/s32cc/
H A Ds32cc_early_clks.c30 int ret; in setup_fxosc() local
32 ret = clk_set_rate(S32CC_CLK_FXOSC, S32CC_FXOSC_FREQ, NULL); in setup_fxosc()
33 if (ret != 0) { in setup_fxosc()
34 return ret; in setup_fxosc()
37 return ret; in setup_fxosc()
42 int ret; in setup_arm_pll() local
44 ret = clk_set_parent(S32CC_CLK_ARM_PLL_MUX, S32CC_CLK_FXOSC); in setup_arm_pll()
45 if (ret != 0) { in setup_arm_pll()
46 return ret; in setup_arm_pll()
49 ret = clk_set_rate(S32CC_CLK_ARM_PLL_VCO, S32CC_ARM_PLL_VCO_FREQ, NULL); in setup_arm_pll()
[all …]
/rk3399_ARM-atf/drivers/st/ddr/phy/phyinit/usercustom/
H A Dddrphy_phyinit_usercustom_saveretregs.c52 int ret; in ddrphy_phyinit_usercustom_saveretregs() local
64 ret = ddrphy_phyinit_trackreg(TMASTER | CSR_PLLCTRL3_ADDR); in ddrphy_phyinit_usercustom_saveretregs()
65 if (ret != 0) { in ddrphy_phyinit_usercustom_saveretregs()
66 return ret; in ddrphy_phyinit_usercustom_saveretregs()
76 ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | r_addr | in ddrphy_phyinit_usercustom_saveretregs()
78 if (ret != 0) { in ddrphy_phyinit_usercustom_saveretregs()
79 return ret; in ddrphy_phyinit_usercustom_saveretregs()
82 ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | r_addr | in ddrphy_phyinit_usercustom_saveretregs()
84 if (ret != 0) { in ddrphy_phyinit_usercustom_saveretregs()
85 return ret; in ddrphy_phyinit_usercustom_saveretregs()
[all …]
H A Dddrphy_phyinit_usercustom_g_waitfwdone.c48 int ret; in ack_message_receipt() local
55 ret = wait_uctwriteprotshadow(true); in ack_message_receipt()
56 if (ret != 0) { in ack_message_receipt()
57 return ret; in ack_message_receipt()
71 int ret; in get_major_message() local
73 ret = wait_uctwriteprotshadow(false); in get_major_message()
74 if (ret != 0) { in get_major_message()
75 return ret; in get_major_message()
82 ret = ack_message_receipt(); in get_major_message()
83 if (ret != 0) { in get_major_message()
[all …]
/rk3399_ARM-atf/drivers/mmc/
H A Dmmc.c58 int ret; in mmc_send_cmd() local
66 ret = ops->send_cmd(&cmd); in mmc_send_cmd()
68 if ((ret == 0) && (r_data != NULL)) { in mmc_send_cmd()
76 if (ret != 0) { in mmc_send_cmd()
77 VERBOSE("Send command %u error: %d\n", idx, ret); in mmc_send_cmd()
80 return ret; in mmc_send_cmd()
89 int ret; in mmc_device_state() local
97 ret = mmc_send_cmd(MMC_CMD(13), rca << RCA_SHIFT_OFFSET, in mmc_device_state()
99 if (ret != 0) { in mmc_device_state()
116 int ret; in mmc_send_part_switch_cmd() local
[all …]
/rk3399_ARM-atf/drivers/ti/ti_sci/
H A Dti_sci.c106 int ret; in ti_sci_get_response() local
110 ret = ti_sci_transport_recv(chan, msg); in ti_sci_get_response()
111 if (ret) { in ti_sci_get_response()
112 ERROR("Message receive failed (%d)\n", ret); in ti_sci_get_response()
113 return ret; in ti_sci_get_response()
156 int ret; in ti_sci_do_xfer() local
161 ret = ti_sci_transport_clear_rx_thread(RX_SECURE_TRANSPORT_CHANNEL_ID); in ti_sci_do_xfer()
162 if (ret) { in ti_sci_do_xfer()
163 ERROR("Could not clear response queue (%d)\n", ret); in ti_sci_do_xfer()
168 ret = ti_sci_transport_send(TX_SECURE_TRANSPORT_CHANNEL_ID, tx_msg); in ti_sci_do_xfer()
[all …]
/rk3399_ARM-atf/drivers/st/ddr/phy/phyinit/src/
H A Dddrphy_phyinit_calcmb.c47 int ret; in ddrphy_phyinit_calcmb() local
91 ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_DRAMTYPE, 0x1U); in ddrphy_phyinit_calcmb()
92 if (ret != 0) { in ddrphy_phyinit_calcmb()
93 return ret; in ddrphy_phyinit_calcmb()
98 ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_DRAMTYPE, 0x2U); in ddrphy_phyinit_calcmb()
99 if (ret != 0) { in ddrphy_phyinit_calcmb()
100 return ret; in ddrphy_phyinit_calcmb()
107 ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_PSTATE, 0U); in ddrphy_phyinit_calcmb()
108 if (ret != 0) { in ddrphy_phyinit_calcmb()
109 return ret; in ddrphy_phyinit_calcmb()
[all …]
H A Dddrphy_phyinit_sequence.c22 int ret; in ddrphy_phyinit_sequence() local
40 ret = ddrphy_phyinit_calcmb(config, &mb_ddr_1d); in ddrphy_phyinit_sequence()
41 if (ret != 0) { in ddrphy_phyinit_sequence()
42 return ret; in ddrphy_phyinit_sequence()
52 ret = ddrphy_phyinit_c_initphyconfig(config, &mb_ddr_1d, &ardptrinitval); in ddrphy_phyinit_sequence()
53 if (ret != 0) { in ddrphy_phyinit_sequence()
54 return ret; in ddrphy_phyinit_sequence()
63 ret = ddrphy_phyinit_reginterface(STOPTRACK, 0U, 0U); in ddrphy_phyinit_sequence()
64 if (ret != 0) { in ddrphy_phyinit_sequence()
65 return ret; in ddrphy_phyinit_sequence()
[all …]
/rk3399_ARM-atf/drivers/mtd/nor/
H A Dspi_nor.c87 int ret; in spi_nor_ready() local
89 ret = spi_nor_read_sr(&sr); in spi_nor_ready()
90 if (ret != 0) { in spi_nor_ready()
91 return ret; in spi_nor_ready()
97 ret = spi_nor_read_fsr(&fsr); in spi_nor_ready()
98 if (ret != 0) { in spi_nor_ready()
99 return ret; in spi_nor_ready()
111 int ret; in spi_nor_wait_ready() local
115 ret = spi_nor_ready(); in spi_nor_wait_ready()
116 if (ret <= 0) { in spi_nor_wait_ready()
[all …]
/rk3399_ARM-atf/plat/st/common/
H A Dstm32cubeprogrammer_uart.c103 int ret; in uart_read_8() local
107 ret = stm32_uart_getc(&handle.uart); in uart_read_8()
108 if (ret == -EAGAIN) { in uart_read_8()
112 } else if (ret < 0) { in uart_read_8()
113 return ret; in uart_read_8()
115 } while (ret == -EAGAIN); in uart_read_8()
117 *byte = (uint8_t)ret; in uart_read_8()
124 int ret; in uart_send_result() local
128 ret = stm32_uart_getc(&handle.uart); in uart_send_result()
129 } while (ret >= 0); in uart_send_result()
[all …]
/rk3399_ARM-atf/plat/allwinner/sun50i_h6/
H A Dsunxi_power.c42 int ret; in rsb_init() local
44 ret = rsb_init_controller(); in rsb_init()
45 if (ret) in rsb_init()
46 return ret; in rsb_init()
49 ret = rsb_set_bus_speed(SUNXI_OSC24M_CLK_IN_HZ, 3000000); in rsb_init()
50 if (ret) in rsb_init()
51 return ret; in rsb_init()
54 ret = rsb_set_device_mode(AXP20X_MODE_RSB << 16 | AXP20X_MODE_REG << 8); in rsb_init()
55 if (ret) in rsb_init()
56 return ret; in rsb_init()
[all …]
/rk3399_ARM-atf/plat/allwinner/sun50i_h616/
H A Dsunxi_power.c53 int ret; in axp_read() local
59 ret = i2c_write(pmic_bus_addr, 0, 0, &reg, 1); in axp_read()
60 if (ret == 0) { in axp_read()
61 ret = i2c_read(pmic_bus_addr, 0, 0, &val, 1); in axp_read()
63 if (ret) { in axp_read()
65 return ret; in axp_read()
73 int ret; in axp_write() local
79 ret = i2c_write(pmic_bus_addr, reg, 1, &val, 1); in axp_write()
80 if (ret) { in axp_write()
84 return ret; in axp_write()
[all …]
/rk3399_ARM-atf/plat/ti/k3/common/
H A Dk3_psci.c44 int core, proc_id, device_id, ret; in k3_pwr_domain_on() local
55 ret = ti_sci_proc_request(proc_id); in k3_pwr_domain_on()
56 if (ret) { in k3_pwr_domain_on()
57 ERROR("Request for processor failed: %d\n", ret); in k3_pwr_domain_on()
61 ret = ti_sci_proc_set_boot_cfg(proc_id, k3_sec_entrypoint, 0, 0); in k3_pwr_domain_on()
62 if (ret) { in k3_pwr_domain_on()
63 ERROR("Request to set core boot address failed: %d\n", ret); in k3_pwr_domain_on()
68 ret = ti_sci_proc_set_boot_ctrl(proc_id, in k3_pwr_domain_on()
72 if (ret) { in k3_pwr_domain_on()
73 ERROR("Request to clear boot configuration failed: %d\n", ret); in k3_pwr_domain_on()
[all …]
/rk3399_ARM-atf/drivers/nxp/sfp/
H A Dfuse_prov.c77 int ret = 0; in prog_srkh() local
79 ret = write_fuses(sfp_ccsr_regs->srk_hash, fuse_hdr->srkh, 8); in prog_srkh()
81 if (ret != 0) { in prog_srkh()
82 ret = (ret == ERROR_ALREADY_BLOWN) ? in prog_srkh()
86 return ret; in prog_srkh()
93 int i, ret = 0; in prog_oemuid() local
99 ret = write_fuses(&sfp_ccsr_regs->oem_uid[i], in prog_oemuid()
102 if (ret != 0) { in prog_oemuid()
103 ret = (ret == ERROR_ALREADY_BLOWN) ? in prog_oemuid()
109 return ret; in prog_oemuid()
[all …]
/rk3399_ARM-atf/plat/imx/imx8ulp/upower/
H A Dupower_hal.c28 int ret = -1; in upower_status() local
33 ret = 0; in upower_status()
49 return ret; in upower_status()
91 int ret, ret_val; in upower_pwm() local
101 ret = upwr_pwm_power_on(&swt, NULL, NULL); in upower_pwm()
103 ret = upwr_pwm_power_off(&swt, NULL, NULL); in upower_pwm()
106 if (ret) { in upower_pwm()
107 NOTICE("%s failed: ret: %d, pwr_on: %d\n", __func__, ret, pwr_on); in upower_pwm()
108 return ret; in upower_pwm()
112 ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, NULL, &ret_val, 1000); in upower_pwm()
[all …]
/rk3399_ARM-atf/plat/xilinx/common/
H A Dplat_fdt.c38 int32_t ret = 0; in is_valid_dtb() local
40 ret = fdt_check_header(fdt); in is_valid_dtb()
41 if (ret != 0) { in is_valid_dtb()
46 ret = fdt_open_into(fdt, fdt, XILINX_OF_BOARD_DTB_MAX_SIZE); in is_valid_dtb()
47 if (ret < 0) { in is_valid_dtb()
48 ERROR("Invalid Device Tree at %p: error %d\n", fdt, ret); in is_valid_dtb()
54 ret = -FDT_ERR_NOTFOUND; in is_valid_dtb()
57 return ret; in is_valid_dtb()
63 int ret = 0; in add_mmap_dynamic_region() local
65 ret = mmap_add_dynamic_region(base_pa, base_va, size, attr); in add_mmap_dynamic_region()
[all …]
/rk3399_ARM-atf/drivers/nxp/i2c/
H A Di2c.c62 int ret; in tx_byte() local
66 ret = wait_for_state(ccsr_i2c, I2C_SR_IF, I2C_SR_IF); in tx_byte()
67 if (ret < 0) { in tx_byte()
69 return ret; in tx_byte()
71 if (ret & I2C_SR_RX_NAK) { in tx_byte()
82 int ret; in gen_stop() local
87 ret = wait_for_state(ccsr_i2c, I2C_SR_IDLE, I2C_SR_BB); in gen_stop()
88 if (ret < 0) { in gen_stop()
91 return ret; in gen_stop()
97 int ret; in i2c_write_addr() local
[all …]
/rk3399_ARM-atf/drivers/mtd/nand/
H A Draw_nand.c90 int ret; in nand_change_read_column_cmd() local
94 ret = nand_send_cmd(NAND_CMD_CHANGE_1ST, 0U); in nand_change_read_column_cmd()
95 if (ret != 0) { in nand_change_read_column_cmd()
96 return ret; in nand_change_read_column_cmd()
107 ret = nand_send_addr(addr[i], 0U); in nand_change_read_column_cmd()
108 if (ret != 0) { in nand_change_read_column_cmd()
109 return ret; in nand_change_read_column_cmd()
113 ret = nand_send_cmd(NAND_CMD_CHANGE_2ND, NAND_TCCS_MIN); in nand_change_read_column_cmd()
114 if (ret != 0) { in nand_change_read_column_cmd()
115 return ret; in nand_change_read_column_cmd()
[all …]
/rk3399_ARM-atf/plat/brcm/board/stingray/driver/
H A Dswreg.c161 int ret; in write_swreg_config() local
166 ret = swreg_poll(); in write_swreg_config()
167 if (ret) { in write_swreg_config()
170 return ret; in write_swreg_config()
172 return ret; in write_swreg_config()
178 int ret; in read_swreg_config() local
183 ret = swreg_poll(); in read_swreg_config()
184 if (ret) { in read_swreg_config()
187 return ret; in read_swreg_config()
192 return ret; in read_swreg_config()
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/rtc/
H A Drtc_mt6359p.c39 int16_t ret; in rtc_enable_k_eosc() local
48 ret = RTC_Write_Trigger(); in rtc_enable_k_eosc()
49 if (ret == 0) { in rtc_enable_k_eosc()
54 ret = RTC_Write_Trigger(); in rtc_enable_k_eosc()
55 if (ret == 0) { in rtc_enable_k_eosc()
60 ret = RTC_Write_Trigger(); in rtc_enable_k_eosc()
61 if (ret == 0) { in rtc_enable_k_eosc()
66 ret = RTC_Write_Trigger(); in rtc_enable_k_eosc()
67 if (ret == 0) { in rtc_enable_k_eosc()
73 ret = RTC_Write_Trigger(); in rtc_enable_k_eosc()
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/apusys/
H A Dapusys.c27 int32_t ret = -1; in apusys_kernel_handler() local
33 ret = apusys_kernel_apusys_rv_pwr_ctrl(APU_PWR_ON); in apusys_kernel_handler()
36 ret = apusys_kernel_apusys_rv_pwr_ctrl(APU_PWR_OFF); in apusys_kernel_handler()
39 ret = apusys_kernel_apusys_rv_setup_reviser(); in apusys_kernel_handler()
42 ret = apusys_kernel_apusys_rv_reset_mp(); in apusys_kernel_handler()
45 ret = apusys_kernel_apusys_rv_setup_boot(); in apusys_kernel_handler()
48 ret = apusys_kernel_apusys_rv_start_mp(); in apusys_kernel_handler()
51 ret = apusys_kernel_apusys_rv_stop_mp(); in apusys_kernel_handler()
54 ret = apusys_devapc_rcx_init(); in apusys_kernel_handler()
57 ret = apusys_kernel_apusys_rv_setup_sec_mem(); in apusys_kernel_handler()
[all …]
/rk3399_ARM-atf/drivers/brcm/
H A Dspi_flash.c58 int ret; in spi_flash_read_id() local
60 ret = spi_flash_cmd(CMD_READ_ID, id, SPI_FLASH_MAX_ID_LEN); in spi_flash_read_id()
61 if (ret < 0) { in spi_flash_read_id()
62 ERROR("SF: Error %d reading JEDEC ID\n", ret); in spi_flash_read_id()
89 int ret; in spi_flash_cmd_wait() local
94 ret = spi_flash_cmd_read(&cmd, 1, &status, 1); in spi_flash_cmd_wait()
95 if (ret < 0) { in spi_flash_cmd_wait()
105 ret = -1; in spi_flash_cmd_wait()
111 return ret; in spi_flash_cmd_wait()
118 int ret; in spi_flash_write_common() local
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/dcm/
H A Dmtk_dcm.c41 bool ret = true; in check_dcm_state() local
43 ret &= dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(); in check_dcm_state()
44 ret &= dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(); in check_dcm_state()
45 ret &= dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(); in check_dcm_state()
47 ret &= dcm_mp_cpusys_top_adb_dcm_is_on(); in check_dcm_state()
48 ret &= dcm_mp_cpusys_top_apb_dcm_is_on(); in check_dcm_state()
49 ret &= dcm_mp_cpusys_top_cpubiu_dcm_is_on(); in check_dcm_state()
50 ret &= dcm_mp_cpusys_top_misc_dcm_is_on(); in check_dcm_state()
51 ret &= dcm_mp_cpusys_top_mp0_qdcm_is_on(); in check_dcm_state()
52 ret &= dcm_cpccfg_reg_emi_wfifo_is_on(); in check_dcm_state()
[all …]
/rk3399_ARM-atf/lib/libfdt/
H A Dfdt_overlay.c48 int path_len = 0, ret; in fdt_overlay_target_offset() local
60 ret = fdt_path_offset(fdt, path); in fdt_overlay_target_offset()
62 ret = path_len; in fdt_overlay_target_offset()
64 ret = fdt_node_offset_by_phandle(fdt, phandle); in fdt_overlay_target_offset()
73 if (ret < 0 && path_len == -FDT_ERR_NOTFOUND) in fdt_overlay_target_offset()
74 ret = -FDT_ERR_BADOVERLAY; in fdt_overlay_target_offset()
77 if (ret < 0) in fdt_overlay_target_offset()
78 return ret; in fdt_overlay_target_offset()
84 return ret; in fdt_overlay_target_offset()
141 int ret; in overlay_adjust_node_phandles() local
[all …]
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/drivers/mce/
H A Dmce.c46 int32_t ret = 0; in mce_command_handler() local
50 ret = nvg_enter_cstate((uint32_t)arg0, (uint32_t)arg1); in mce_command_handler()
51 if (ret < 0) { in mce_command_handler()
52 ERROR("%s: enter_cstate failed(%d)\n", __func__, ret); in mce_command_handler()
58 ret = nvg_is_sc7_allowed(); in mce_command_handler()
59 if (ret < 0) { in mce_command_handler()
60 ERROR("%s: is_sc7_allowed failed(%d)\n", __func__, ret); in mce_command_handler()
66 ret = nvg_online_core((uint32_t)arg0); in mce_command_handler()
67 if (ret < 0) { in mce_command_handler()
68 ERROR("%s: online_core failed(%d)\n", __func__, ret); in mce_command_handler()
[all …]
/rk3399_ARM-atf/plat/ti/k3low/common/
H A Dam62l_bl31_setup.c30 int ret; in ti_soc_init() local
34 ret = ti_sci_boot_notification(); in ti_soc_init()
35 if (ret != 0) { in ti_soc_init()
36 ERROR("%s: Failed to receive boot notification (%d)\n", __func__, ret); in ti_soc_init()
37 return ret; in ti_soc_init()
40 ret = ti_sci_get_revision(&version); in ti_soc_init()
41 if (ret != 0) { in ti_soc_init()
42 ERROR("%s: Failed to get revision (%d)\n", __func__, ret); in ti_soc_init()
43 return ret; in ti_soc_init()
51 ret = ti_sci_proc_request(PLAT_PROC_START_ID); in ti_soc_init()
[all …]

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