Merge changes from topic "upstream_deassert_ddr_reset" into integration

* changes:
feat(s32g274ardb): add DDR clock source support
feat(s32g274ardb): add mc_rgm_release_periph func

feat(s32g274ardb): add DDR clock source support

Introduce support to configure DDR clock
source and safely deasserting the reset
signal for the DDR controller.

These utilities are required before
i

feat(s32g274ardb): add DDR clock source support

Introduce support to configure DDR clock
source and safely deasserting the reset
signal for the DDR controller.

These utilities are required before
initializing the DDR subsystem.

Change-Id: I48cc984f73fca5cde1b81e9075488fd5bed420d6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

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Merge changes from topic "s32g274a/sd_mov_imm_fixes" into integration

* changes:
fix(s32g274a): reduce the uSDHC clock to 200MHz
refactor(s32g274a): replace mov/movk with mov_imm

fix(s32g274a): reduce the uSDHC clock to 200MHz

Reduce the uSDHC clock to 200 MHz to ensure compatibility with the uSDHC
driver and alignment with the S32G274A data sheet.

Change-Id: Ic67c750561890

fix(s32g274a): reduce the uSDHC clock to 200MHz

Reduce the uSDHC clock to 200 MHz to ensure compatibility with the uSDHC
driver and alignment with the S32G274A data sheet.

Change-Id: Ic67c75056189075b1ba260e32426421e1e79a2e7
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge changes from topic "nxp-clk/add_usdhc_clock" into integration

* changes:
feat(s32g274a): enable sdhc clock
feat(nxp-clk): add clock modules for uSDHC
feat(nxp-clk): get MC_CGM divider's

Merge changes from topic "nxp-clk/add_usdhc_clock" into integration

* changes:
feat(s32g274a): enable sdhc clock
feat(nxp-clk): add clock modules for uSDHC
feat(nxp-clk): get MC_CGM divider's parent
feat(nxp-clk): get MC_CGM divider's rate
feat(nxp-clk): set MC_CGM divider's rate
feat(nxp-clk): enable MC_CGM dividers
feat(nxp-clk): get parent for the fixed dividers
feat(nxp-clk): set the rate for partition objects
feat(nxp-clk): add clock objects for CGM dividers
feat(nxp-clk): add base address for PERIPH_DFS

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feat(s32g274a): enable sdhc clock

The uSDHC module clock must be enabled to use the SD/eMMC storage from
where the BL2 is expected to load images for the next boot stages.

Change-Id: Ib1cc7d5dda7a4

feat(s32g274a): enable sdhc clock

The uSDHC module clock must be enabled to use the SD/eMMC storage from
where the BL2 is expected to load images for the next boot stages.

Change-Id: Ib1cc7d5dda7a4283a29716f5b3d776048bd5b7ba
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge changes from topic "nxp-s32g274a/enable-mmu" into integration

* changes:
feat(s32g274a): split early clock initialization
feat(s32g274a): enable MMU for BL31 stage
feat(s32g274a): dynami

Merge changes from topic "nxp-s32g274a/enable-mmu" into integration

* changes:
feat(s32g274a): split early clock initialization
feat(s32g274a): enable MMU for BL31 stage
feat(s32g274a): dynamically map GIC regions
feat(s32g274a): enable MMU for BL2 stage
feat(s32g274a): dynamically map siul2 and fip img
feat(s32g274a): map each image before its loading
feat(nxp-clk): dynamic map of the clock modules
feat(s32g274a): increase the number of MMU regions
feat(s32g274a): add console mapping

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feat(s32g274a): split early clock initialization

Initializing all early clocks before the MMU is enabled can impact boot
time. Therefore, splitting the setup into A53 clocks and peripheral
clocks ca

feat(s32g274a): split early clock initialization

Initializing all early clocks before the MMU is enabled can impact boot
time. Therefore, splitting the setup into A53 clocks and peripheral
clocks can be beneficial, with the peripheral clocks configured after
fully initializing the MMU.

Change-Id: I19644227b66effab8e2c43e64e057ea0c8625ebc
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): dynamic map of the clock modules

Add all clock modules as entries in MMU using dynamic regions.

Change-Id: I56f724ced4bd024554c7b38afd14ea420de80cc6
Signed-off-by: Ghennadi Procopciu

feat(nxp-clk): dynamic map of the clock modules

Add all clock modules as entries in MMU using dynamic regions.

Change-Id: I56f724ced4bd024554c7b38afd14ea420de80cc6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge changes from topic "nxp-clk/add_ddr_clk" into integration

* changes:
fix(nxp-clk): function parameter should not be modified
feat(nxp-clk): enable the DDR clock
feat(nxp-clk): add object

Merge changes from topic "nxp-clk/add_ddr_clk" into integration

* changes:
fix(nxp-clk): function parameter should not be modified
feat(nxp-clk): enable the DDR clock
feat(nxp-clk): add objects needed for DDR clock
feat(nxp-clk): setup the DDR PLL
feat(nxp-clk): add MC_ME utilities
feat(nxp-clk): add partition reset utilities
feat(nxp-clk): add partitions objects

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feat(nxp-clk): enable the DDR clock

Enable the DDR clock by setting up its reset block, the associated
partition and configuring the clock tree above the MC_CGM mux.

Change-Id: Idfed24b3e74a189df87

feat(nxp-clk): enable the DDR clock

Enable the DDR clock by setting up its reset block, the associated
partition and configuring the clock tree above the MC_CGM mux.

Change-Id: Idfed24b3e74a189df87f9782886a91b906cd2022
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): setup the DDR PLL

Add the DDR PLL instance and configure it to operate at its maximum
allowed frequency.

Change-Id: I96efd68687de78f70759f631d10a0f611c234c8d
Signed-off-by: Ghennadi

feat(nxp-clk): setup the DDR PLL

Add the DDR PLL instance and configure it to operate at its maximum
allowed frequency.

Change-Id: I96efd68687de78f70759f631d10a0f611c234c8d
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge changes from topic "nxp-drivers/add-get-parent-callback" into integration

* changes:
feat(nxp-clk): refactor clock enablement
feat(nxp-clk): add get_parent callback
fix(nxp-clk): broken

Merge changes from topic "nxp-drivers/add-get-parent-callback" into integration

* changes:
feat(nxp-clk): refactor clock enablement
feat(nxp-clk): add get_parent callback
fix(nxp-clk): broken UART clock initalization

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feat(nxp-clk): refactor clock enablement

Simplify the clock enablement mechanism from a usage perspective. With
this new approach, enabling a clock cascades the turn-on sequence of all
its parent cl

feat(nxp-clk): refactor clock enablement

Simplify the clock enablement mechanism from a usage perspective. With
this new approach, enabling a clock cascades the turn-on sequence of all
its parent clocks in the clock tree. Therefore, enabling the A53 clock
will also turn on the A53 PLL and the oscillator that feeds it.

Change-Id: Ifc2bee3e9edbb4baced34f9e809a961562f7d0a6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge changes from topic "nxp-drivers/add-linflex-clk" into integration

* changes:
feat(nxp-clk): enable UART clock
feat(nxp-clk): add PERIPH PLL enablement

feat(nxp-clk): enable UART clock

Before this change, the internal oscillator clocked the UART with a
frequency of 48MHz. With the necessary support added, the UART clock
rate is increased to 125MHz

feat(nxp-clk): enable UART clock

Before this change, the internal oscillator clocked the UART with a
frequency of 48MHz. With the necessary support added, the UART clock
rate is increased to 125MHz by changing the clock source from FIRC to
PERIPH PLL PHI3.

Change-Id: I3160dc6860ebf441c9bea8eaf9d8d12de48bd647
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add PERIPH PLL enablement

Peripheral PLL is one of the platform's PLLs, providing a clock for
peripherals such as UART, QSPI, uSDHC, SPI and CAN. Its source can be
either the FIRC or

feat(nxp-clk): add PERIPH PLL enablement

Peripheral PLL is one of the platform's PLLs, providing a clock for
peripherals such as UART, QSPI, uSDHC, SPI and CAN. Its source can be
either the FIRC or FXOSC oscillators. It has eight outputs (PHIs) and
their frequencies can be controlled programmatically using output
dividers. An additional output clocks the PERIPH DFS using the VCO
frequency of the PERIPH PLL.

Change-Id: I637294b2da94f35e95dc1750dad36c129a276bb9
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge changes from topic "nxp-s32g2/add-xbar-clk" into integration

* changes:
feat(nxp-clk): enable the XBAR clock
feat(nxp-clk): add dependencies for the XBAR clock
feat(nxp-clk): add CGM0 in

Merge changes from topic "nxp-s32g2/add-xbar-clk" into integration

* changes:
feat(nxp-clk): enable the XBAR clock
feat(nxp-clk): add dependencies for the XBAR clock
feat(nxp-clk): add CGM0 instance
feat(nxp-clk): add DFS module enablement
feat(nxp-clk): add clock objects for ARM DFS
refactor(nxp-clk): organize early clocks in groups

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feat(nxp-clk): enable the XBAR clock

Enable the XBAR clock, which is the primary system clock.

Change-Id: Idaafbb8894472b10e1ed8a35b25967c82106e667
Signed-off-by: Ghennadi Procopciuc <ghennadi.proc

feat(nxp-clk): enable the XBAR clock

Enable the XBAR clock, which is the primary system clock.

Change-Id: Idaafbb8894472b10e1ed8a35b25967c82106e667
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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refactor(nxp-clk): organize early clocks in groups

This reduces the length of the s32cc_init_early_clks function and offers
space for more early clocks to be added.

Change-Id: I0d11b97779433a6b15cd

refactor(nxp-clk): organize early clocks in groups

This reduces the length of the s32cc_init_early_clks function and offers
space for more early clocks to be added.

Change-Id: I0d11b97779433a6b15cd76c36aefbb7b92381067
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge changes from topic "enable_a53_clk" into integration

* changes:
feat(nxp-clk): enable the A53 clock
feat(nxp-clk): add ARM PLL ODIV enablement
feat(nxp-clk): add ARM PLL enablement
fea

Merge changes from topic "enable_a53_clk" into integration

* changes:
feat(nxp-clk): enable the A53 clock
feat(nxp-clk): add ARM PLL ODIV enablement
feat(nxp-clk): add ARM PLL enablement
feat(nxp-clk): set rate for clock muxes

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feat(nxp-clk): enable the A53 clock

Enable the A53 clock at 1GHz, the maximum frequency on S32G2 SoCs.

Change-Id: Ife96792faf8f3f46965bdcf4df75fcca5e39dc6e
Signed-off-by: Ghennadi Procopciuc <ghenn

feat(nxp-clk): enable the A53 clock

Enable the A53 clock at 1GHz, the maximum frequency on S32G2 SoCs.

Change-Id: Ife96792faf8f3f46965bdcf4df75fcca5e39dc6e
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add ARM PLL ODIV enablement

Enable the PLL dividers using their memory-mapped interface. Otherwise,
the clock will not be propagated to downstream clock modules.

Change-Id: I39115cb2

feat(nxp-clk): add ARM PLL ODIV enablement

Enable the PLL dividers using their memory-mapped interface. Otherwise,
the clock will not be propagated to downstream clock modules.

Change-Id: I39115cb2cb754cee87d7b6b4aa7502c3f1ef37ce
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add ARM PLL enablement

Add the low-level implementation to enable the ARM PLL oscillator, which
is disabled by default when booting the SoC. It will be used by PLL
diviers, for which

feat(nxp-clk): add ARM PLL enablement

Add the low-level implementation to enable the ARM PLL oscillator, which
is disabled by default when booting the SoC. It will be used by PLL
diviers, for which support will be added later.

Change-Id: I964fa7374ea9a08c695009176eade01003c1d6c2
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): set rate for clock muxes

The clock muxes will simply pass the set rate request to the clock
module connected to its source, as they do not alter the frequency.

Change-Id: I5fda8fffa0

feat(nxp-clk): set rate for clock muxes

The clock muxes will simply pass the set rate request to the clock
module connected to its source, as they do not alter the frequency.

Change-Id: I5fda8fffa0f46a4be96deac4d6a5a880c9f86ccf
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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