21 	uint32_t ret = NO_ERR;  in execute_2d_training()  local
25 	ret = load_phy_image(IMEM_START_ADDR, config->imem_2d_size,  in execute_2d_training()
27 	if (ret != NO_ERR) {  in execute_2d_training()
28 		return ret;  in execute_2d_training()
34 	ret = load_phy_image(DMEM_START_ADDR, config->dmem_2d_size,  in execute_2d_training()
36 	if (ret != NO_ERR) {  in execute_2d_training()
37 		return ret;  in execute_2d_training()
45 	ret = wait_firmware_execution();  in execute_2d_training()
46 	if (ret != NO_ERR) {  in execute_2d_training()
47 		return ret;  in execute_2d_training()
58 	return ret;  in execute_2d_training()
64 	uint32_t ret = NO_ERR;  in execute_training()  local
67 	ret = load_dq_cfg(config->dq_swap_size, config->dq_swap);  in execute_training()
68 	if (ret != NO_ERR) {  in execute_training()
69 		return ret;  in execute_training()
73 	ret = load_register_cfg_16(config->phy_size, config->phy);  in execute_training()
74 	if (ret != NO_ERR) {  in execute_training()
75 		return ret;  in execute_training()
83 	ret = load_phy_image(IMEM_START_ADDR, config->imem_1d_size,  in execute_training()
85 	if (ret != NO_ERR) {  in execute_training()
86 		return ret;  in execute_training()
92 	ret = load_phy_image(DMEM_START_ADDR, config->dmem_1d_size,  in execute_training()
94 	if (ret != NO_ERR) {  in execute_training()
95 		return ret;  in execute_training()
103 	ret = wait_firmware_execution();  in execute_training()
105 	if (ret != NO_ERR) {  in execute_training()
106 		return ret;  in execute_training()
125 		ret = execute_2d_training(config);  in execute_training()
126 		if (ret != NO_ERR) {  in execute_training()
127 			return ret;  in execute_training()
133 	ret = load_register_cfg_16(config->pie_size, config->pie);  in execute_training()
135 	return ret;  in execute_training()
141 	uint32_t ret = NO_ERR;  in ddr_init_cfg()  local
144 	ret = ddrc_init_cfg(config);  in ddr_init_cfg()
145 	if (ret != NO_ERR) {  in ddr_init_cfg()
146 		return ret;  in ddr_init_cfg()
150 	ret = set_axi_parity();  in ddr_init_cfg()
151 	if (ret != NO_ERR) {  in ddr_init_cfg()
152 		return ret;  in ddr_init_cfg()
156 	ret = execute_training(config);  in ddr_init_cfg()
157 	if (ret != NO_ERR) {  in ddr_init_cfg()
158 		return ret;  in ddr_init_cfg()
162 	ret = post_train_setup((uint8_t)(ADJUST_DDRC_MASK));  in ddr_init_cfg()
164 	return ret;  in ddr_init_cfg()