1*bc9410e2SGarmin Chang /* 2*bc9410e2SGarmin Chang * Copyright (c) 2022, MediaTek Inc. All rights reserved. 3*bc9410e2SGarmin Chang * 4*bc9410e2SGarmin Chang * SPDX-License-Identifier: BSD-3-Clause 5*bc9410e2SGarmin Chang */ 6*bc9410e2SGarmin Chang 7*bc9410e2SGarmin Chang #include <common/debug.h> 8*bc9410e2SGarmin Chang #include <lib/mmio.h> 9*bc9410e2SGarmin Chang #include <lib/mtk_init/mtk_init.h> 10*bc9410e2SGarmin Chang #include <mtk_dcm.h> 11*bc9410e2SGarmin Chang #include <mtk_dcm_utils.h> 12*bc9410e2SGarmin Chang dcm_armcore(bool mode)13*bc9410e2SGarmin Changstatic void dcm_armcore(bool mode) 14*bc9410e2SGarmin Chang { 15*bc9410e2SGarmin Chang dcm_mp_cpusys_top_bus_pll_div_dcm(mode); 16*bc9410e2SGarmin Chang dcm_mp_cpusys_top_cpu_pll_div_0_dcm(mode); 17*bc9410e2SGarmin Chang dcm_mp_cpusys_top_cpu_pll_div_1_dcm(mode); 18*bc9410e2SGarmin Chang } 19*bc9410e2SGarmin Chang dcm_mcusys(bool on)20*bc9410e2SGarmin Changstatic void dcm_mcusys(bool on) 21*bc9410e2SGarmin Chang { 22*bc9410e2SGarmin Chang dcm_mp_cpusys_top_adb_dcm(on); 23*bc9410e2SGarmin Chang dcm_mp_cpusys_top_apb_dcm(on); 24*bc9410e2SGarmin Chang dcm_mp_cpusys_top_cpubiu_dcm(on); 25*bc9410e2SGarmin Chang dcm_mp_cpusys_top_misc_dcm(on); 26*bc9410e2SGarmin Chang dcm_mp_cpusys_top_mp0_qdcm(on); 27*bc9410e2SGarmin Chang 28*bc9410e2SGarmin Chang /* CPCCFG_REG */ 29*bc9410e2SGarmin Chang dcm_cpccfg_reg_emi_wfifo(on); 30*bc9410e2SGarmin Chang dcm_mp_cpusys_top_last_cor_idle_dcm(on); 31*bc9410e2SGarmin Chang } 32*bc9410e2SGarmin Chang dcm_stall(bool on)33*bc9410e2SGarmin Changstatic void dcm_stall(bool on) 34*bc9410e2SGarmin Chang { 35*bc9410e2SGarmin Chang dcm_mp_cpusys_top_core_stall_dcm(on); 36*bc9410e2SGarmin Chang dcm_mp_cpusys_top_fcm_stall_dcm(on); 37*bc9410e2SGarmin Chang } 38*bc9410e2SGarmin Chang check_dcm_state(void)39*bc9410e2SGarmin Changstatic bool check_dcm_state(void) 40*bc9410e2SGarmin Chang { 41*bc9410e2SGarmin Chang bool ret = true; 42*bc9410e2SGarmin Chang 43*bc9410e2SGarmin Chang ret &= dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(); 44*bc9410e2SGarmin Chang ret &= dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(); 45*bc9410e2SGarmin Chang ret &= dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(); 46*bc9410e2SGarmin Chang 47*bc9410e2SGarmin Chang ret &= dcm_mp_cpusys_top_adb_dcm_is_on(); 48*bc9410e2SGarmin Chang ret &= dcm_mp_cpusys_top_apb_dcm_is_on(); 49*bc9410e2SGarmin Chang ret &= dcm_mp_cpusys_top_cpubiu_dcm_is_on(); 50*bc9410e2SGarmin Chang ret &= dcm_mp_cpusys_top_misc_dcm_is_on(); 51*bc9410e2SGarmin Chang ret &= dcm_mp_cpusys_top_mp0_qdcm_is_on(); 52*bc9410e2SGarmin Chang ret &= dcm_cpccfg_reg_emi_wfifo_is_on(); 53*bc9410e2SGarmin Chang ret &= dcm_mp_cpusys_top_last_cor_idle_dcm_is_on(); 54*bc9410e2SGarmin Chang 55*bc9410e2SGarmin Chang ret &= dcm_mp_cpusys_top_core_stall_dcm_is_on(); 56*bc9410e2SGarmin Chang ret &= dcm_mp_cpusys_top_fcm_stall_dcm_is_on(); 57*bc9410e2SGarmin Chang 58*bc9410e2SGarmin Chang return ret; 59*bc9410e2SGarmin Chang } 60*bc9410e2SGarmin Chang dcm_check_state(uintptr_t addr,unsigned int mask,unsigned int compare)61*bc9410e2SGarmin Changbool dcm_check_state(uintptr_t addr, unsigned int mask, unsigned int compare) 62*bc9410e2SGarmin Chang { 63*bc9410e2SGarmin Chang return ((mmio_read_32(addr) & mask) == compare); 64*bc9410e2SGarmin Chang } 65*bc9410e2SGarmin Chang dcm_set_init(void)66*bc9410e2SGarmin Changint dcm_set_init(void) 67*bc9410e2SGarmin Chang { 68*bc9410e2SGarmin Chang int ret; 69*bc9410e2SGarmin Chang 70*bc9410e2SGarmin Chang dcm_armcore(true); 71*bc9410e2SGarmin Chang dcm_mcusys(true); 72*bc9410e2SGarmin Chang dcm_stall(true); 73*bc9410e2SGarmin Chang 74*bc9410e2SGarmin Chang if (check_dcm_state() == false) { 75*bc9410e2SGarmin Chang ERROR("Failed to set default dcm on!!\n"); 76*bc9410e2SGarmin Chang ret = -1; 77*bc9410e2SGarmin Chang } else { 78*bc9410e2SGarmin Chang INFO("%s, dcm pass\n", __func__); 79*bc9410e2SGarmin Chang ret = 0; 80*bc9410e2SGarmin Chang } 81*bc9410e2SGarmin Chang 82*bc9410e2SGarmin Chang return ret; 83*bc9410e2SGarmin Chang } 84*bc9410e2SGarmin Chang MTK_PLAT_SETUP_0_INIT(dcm_set_init); 85