Lines Matching refs:ret
30 int ret; in setup_fxosc() local
32 ret = clk_set_rate(S32CC_CLK_FXOSC, S32CC_FXOSC_FREQ, NULL); in setup_fxosc()
33 if (ret != 0) { in setup_fxosc()
34 return ret; in setup_fxosc()
37 return ret; in setup_fxosc()
42 int ret; in setup_arm_pll() local
44 ret = clk_set_parent(S32CC_CLK_ARM_PLL_MUX, S32CC_CLK_FXOSC); in setup_arm_pll()
45 if (ret != 0) { in setup_arm_pll()
46 return ret; in setup_arm_pll()
49 ret = clk_set_rate(S32CC_CLK_ARM_PLL_VCO, S32CC_ARM_PLL_VCO_FREQ, NULL); in setup_arm_pll()
50 if (ret != 0) { in setup_arm_pll()
51 return ret; in setup_arm_pll()
54 ret = clk_set_rate(S32CC_CLK_ARM_PLL_PHI0, S32CC_ARM_PLL_PHI0_FREQ, NULL); in setup_arm_pll()
55 if (ret != 0) { in setup_arm_pll()
56 return ret; in setup_arm_pll()
59 return ret; in setup_arm_pll()
64 int ret; in setup_periph_pll() local
66 ret = clk_set_parent(S32CC_CLK_PERIPH_PLL_MUX, S32CC_CLK_FXOSC); in setup_periph_pll()
67 if (ret != 0) { in setup_periph_pll()
68 return ret; in setup_periph_pll()
71 ret = clk_set_rate(S32CC_CLK_PERIPH_PLL_VCO, S32CC_PERIPH_PLL_VCO_FREQ, NULL); in setup_periph_pll()
72 if (ret != 0) { in setup_periph_pll()
73 return ret; in setup_periph_pll()
76 ret = clk_set_rate(S32CC_CLK_PERIPH_PLL_PHI3, S32CC_PERIPH_PLL_PHI3_FREQ, NULL); in setup_periph_pll()
77 if (ret != 0) { in setup_periph_pll()
78 return ret; in setup_periph_pll()
81 return ret; in setup_periph_pll()
86 int ret; in enable_a53_clk() local
88 ret = clk_set_parent(S32CC_CLK_MC_CGM1_MUX0, S32CC_CLK_ARM_PLL_PHI0); in enable_a53_clk()
89 if (ret != 0) { in enable_a53_clk()
90 return ret; in enable_a53_clk()
93 ret = clk_set_rate(S32CC_CLK_A53_CORE, S32CC_A53_FREQ, NULL); in enable_a53_clk()
94 if (ret != 0) { in enable_a53_clk()
95 return ret; in enable_a53_clk()
98 ret = clk_enable(S32CC_CLK_A53_CORE); in enable_a53_clk()
99 if (ret != 0) { in enable_a53_clk()
100 return ret; in enable_a53_clk()
103 return ret; in enable_a53_clk()
108 int ret; in enable_xbar_clk() local
110 ret = clk_set_parent(S32CC_CLK_MC_CGM0_MUX0, S32CC_CLK_ARM_PLL_DFS1); in enable_xbar_clk()
111 if (ret != 0) { in enable_xbar_clk()
112 return ret; in enable_xbar_clk()
115 ret = clk_set_rate(S32CC_CLK_XBAR_2X, S32CC_XBAR_2X_FREQ, NULL); in enable_xbar_clk()
116 if (ret != 0) { in enable_xbar_clk()
117 return ret; in enable_xbar_clk()
120 ret = clk_enable(S32CC_CLK_ARM_PLL_DFS1); in enable_xbar_clk()
121 if (ret != 0) { in enable_xbar_clk()
122 return ret; in enable_xbar_clk()
125 ret = clk_enable(S32CC_CLK_XBAR_2X); in enable_xbar_clk()
126 if (ret != 0) { in enable_xbar_clk()
127 return ret; in enable_xbar_clk()
130 return ret; in enable_xbar_clk()
135 int ret; in enable_uart_clk() local
137 ret = clk_set_parent(S32CC_CLK_MC_CGM0_MUX8, S32CC_CLK_PERIPH_PLL_PHI3); in enable_uart_clk()
138 if (ret != 0) { in enable_uart_clk()
139 return ret; in enable_uart_clk()
142 ret = clk_enable(S32CC_CLK_LINFLEX_BAUD); in enable_uart_clk()
143 if (ret != 0) { in enable_uart_clk()
144 return ret; in enable_uart_clk()
147 return ret; in enable_uart_clk()
152 int ret; in setup_ddr_pll() local
154 ret = clk_set_parent(S32CC_CLK_DDR_PLL_MUX, S32CC_CLK_FXOSC); in setup_ddr_pll()
155 if (ret != 0) { in setup_ddr_pll()
156 return ret; in setup_ddr_pll()
159 ret = clk_set_rate(S32CC_CLK_DDR_PLL_VCO, S32CC_DDR_PLL_VCO_FREQ, NULL); in setup_ddr_pll()
160 if (ret != 0) { in setup_ddr_pll()
161 return ret; in setup_ddr_pll()
164 ret = clk_set_rate(S32CC_CLK_DDR_PLL_PHI0, S32CC_DDR_PLL_PHI0_FREQ, NULL); in setup_ddr_pll()
165 if (ret != 0) { in setup_ddr_pll()
166 return ret; in setup_ddr_pll()
169 return ret; in setup_ddr_pll()
174 int ret; in enable_ddr_clk() local
176 ret = clk_set_parent(S32CC_CLK_MC_CGM5_MUX0, S32CC_CLK_DDR_PLL_PHI0); in enable_ddr_clk()
177 if (ret != 0) { in enable_ddr_clk()
178 return ret; in enable_ddr_clk()
181 ret = clk_enable(S32CC_CLK_DDR); in enable_ddr_clk()
182 if (ret != 0) { in enable_ddr_clk()
183 return ret; in enable_ddr_clk()
186 return ret; in enable_ddr_clk()
191 int ret; in enable_usdhc_clk() local
193 ret = clk_set_parent(S32CC_CLK_MC_CGM0_MUX14, in enable_usdhc_clk()
195 if (ret != 0) { in enable_usdhc_clk()
196 return ret; in enable_usdhc_clk()
199 ret = clk_set_rate(S32CC_CLK_PERIPH_PLL_DFS3, in enable_usdhc_clk()
201 if (ret != 0) { in enable_usdhc_clk()
202 return ret; in enable_usdhc_clk()
205 ret = clk_set_rate(S32CC_CLK_USDHC, S32CC_USDHC_FREQ, NULL); in enable_usdhc_clk()
206 if (ret != 0) { in enable_usdhc_clk()
207 return ret; in enable_usdhc_clk()
210 ret = clk_enable(S32CC_CLK_USDHC); in enable_usdhc_clk()
211 if (ret != 0) { in enable_usdhc_clk()
212 return ret; in enable_usdhc_clk()
215 return ret; in enable_usdhc_clk()
244 int ret; in s32cc_init_core_clocks() local
246 ret = s32cc_clk_register_drv(false); in s32cc_init_core_clocks()
247 if (ret != 0) { in s32cc_init_core_clocks()
248 return ret; in s32cc_init_core_clocks()
251 ret = setup_fxosc(); in s32cc_init_core_clocks()
252 if (ret != 0) { in s32cc_init_core_clocks()
253 return ret; in s32cc_init_core_clocks()
256 ret = setup_arm_pll(); in s32cc_init_core_clocks()
257 if (ret != 0) { in s32cc_init_core_clocks()
258 return ret; in s32cc_init_core_clocks()
261 ret = enable_a53_clk(); in s32cc_init_core_clocks()
262 if (ret != 0) { in s32cc_init_core_clocks()
263 return ret; in s32cc_init_core_clocks()
266 ret = enable_xbar_clk(); in s32cc_init_core_clocks()
267 if (ret != 0) { in s32cc_init_core_clocks()
268 return ret; in s32cc_init_core_clocks()
271 return ret; in s32cc_init_core_clocks()
276 int ret; in s32cc_init_early_clks() local
278 ret = s32cc_clk_register_drv(true); in s32cc_init_early_clks()
279 if (ret != 0) { in s32cc_init_early_clks()
280 return ret; in s32cc_init_early_clks()
283 ret = setup_periph_pll(); in s32cc_init_early_clks()
284 if (ret != 0) { in s32cc_init_early_clks()
285 return ret; in s32cc_init_early_clks()
288 ret = enable_uart_clk(); in s32cc_init_early_clks()
289 if (ret != 0) { in s32cc_init_early_clks()
290 return ret; in s32cc_init_early_clks()
293 ret = setup_ddr_pll(); in s32cc_init_early_clks()
294 if (ret != 0) { in s32cc_init_early_clks()
295 return ret; in s32cc_init_early_clks()
298 ret = enable_ddr_clk(); in s32cc_init_early_clks()
299 if (ret != 0) { in s32cc_init_early_clks()
300 return ret; in s32cc_init_early_clks()
303 ret = enable_usdhc_clk(); in s32cc_init_early_clks()
304 if (ret != 0) { in s32cc_init_early_clks()
305 return ret; in s32cc_init_early_clks()
308 return ret; in s32cc_init_early_clks()