| #
381d6850 |
| 18-Oct-2021 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes Id7d4f5df,If82542cc,I0ba80057,I75a443db,Ifa18b4fc, ... into integration
* changes:
feat(nxp/common/ocram): add driver for OCRAM initialization
feat(plat/nxp/common): add EESR regis
Merge changes Id7d4f5df,If82542cc,I0ba80057,I75a443db,Ifa18b4fc, ... into integration
* changes:
feat(nxp/common/ocram): add driver for OCRAM initialization
feat(plat/nxp/common): add EESR register definition
fix(plat/nxp/ls1028a): fix compile error when enable fuse provision
fix(drivers/nxp/sfp): fix compile warning
fix(plat/nxp/ls1028a): define endianness of scfg and gpio
fix(nxp/scfg): fix endianness checking
show more ...
|
| #
3239a175 |
| 27-Sep-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
fix(drivers/nxp/sfp): fix compile warning
Fix compile warning that ‘mask’ may be used uninitialized.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I75a443dbc36d7bd174fe317616fd95cd09630
fix(drivers/nxp/sfp): fix compile warning
Fix compile warning that ‘mask’ may be used uninitialized.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I75a443dbc36d7bd174fe317616fd95cd096306fc
show more ...
|
| #
9719e19a |
| 24-Mar-2021 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes I500ddbe9,I9c10dac9,I53bfff85,I06f7594d,I24bff8d4, ... into integration
* changes:
nxp lx2160a-aqds: new plat based on soc lx2160a
NXP lx2160a-rdb: new plat based on SoC lx2160a
Merge changes I500ddbe9,I9c10dac9,I53bfff85,I06f7594d,I24bff8d4, ... into integration
* changes:
nxp lx2160a-aqds: new plat based on soc lx2160a
NXP lx2160a-rdb: new plat based on SoC lx2160a
nxp lx2162aqds: new plat based on soc lx2160a
nxp: errata handling at soc level for lx2160a
nxp: make file for loading additional ddr image
nxp: adding support of soc lx2160a
nxp: deflt hdr files for soc & their platforms
nxp: platform files for bl2 and bl31 setup
nxp: warm reset support to retain ddr content
nxp: nv storage api on platforms
nxp: supports two mode of trusted board boot
nxp: fip-handler for additional fip_fuse.bin
nxp: fip-handler for additional ddr-fip.bin
nxp: image loader for loading fip image
nxp: svp & sip smc handling
nxp: psci platform functions used by lib/psci
nxp: helper function used by plat & common code
nxp: add data handler used by bl31
nxp: adding the driver.mk file
nxp-tool: for creating pbl file from bl2
nxp: adding the smmu driver
nxp: cot using nxp internal and mbedtls
nxp:driver for crypto h/w accelerator caam
nxp:add driver support for sd and emmc
nxp:add qspi driver
nxp: add flexspi driver support
nxp: adding gic apis for nxp soc
nxp: gpio driver support
nxp: added csu driver
nxp: driver pmu for nxp soc
nxp: ddr driver enablement for nxp layerscape soc
nxp: i2c driver support.
NXP: Driver for NXP Security Monitor
NXP: SFP driver support for NXP SoC
NXP: Interconnect API based on ARM CCN-CCI driver
NXP: TZC API to configure ddr region
NXP: Timer API added to enable ARM generic timer
nxp: add dcfg driver
nxp:add console driver for nxp platform
tools: add mechanism to allow platform specific image UUID
tbbr-cot: conditional definition for the macro
tbbr-cot: fix the issue of compiling time define
cert_create: updated tool for platform defined certs, keys & extensions
tbbr-tools: enable override TRUSTED_KEY_CERT
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| #
3979c6d9 |
| 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
NXP: SFP driver support for NXP SoC
NXP Security Fuse Processor is used to read and write
fuses.
- Fuses once written, are cannot be un-done.
- Used as trust anchor for monotonic counter,
differen
NXP: SFP driver support for NXP SoC
NXP Security Fuse Processor is used to read and write
fuses.
- Fuses once written, are cannot be un-done.
- Used as trust anchor for monotonic counter,
different platform keys etc.
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I347e806dd87078150fbbbfc28355bb44d9eacb9c
show more ...
|