1 /*
2 * Copyright (c) 2017-2025, Arm Limited. All rights reserved.
3 * Copyright (c) 2018, Icenowy Zheng <icenowy@aosc.io>
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <errno.h>
9 #include <string.h>
10
11 #include <arch_helpers.h>
12 #include <common/debug.h>
13 #include <common/fdt_wrappers.h>
14 #include <drivers/allwinner/axp.h>
15 #include <drivers/allwinner/sunxi_rsb.h>
16 #include <drivers/mentor/mi2cv.h>
17 #include <lib/mmio.h>
18 #include <libfdt.h>
19
20 #include <sunxi_cpucfg.h>
21 #include <sunxi_def.h>
22 #include <sunxi_mmap.h>
23 #include <sunxi_private.h>
24
25 static uint16_t pmic_bus_addr;
26 static uint8_t rsb_rt_addr;
27
is_using_rsb(void)28 static bool is_using_rsb(void)
29 {
30 return rsb_rt_addr != 0;
31 }
32
33 static enum pmic_type {
34 UNKNOWN,
35 AXP305,
36 AXP313,
37 AXP717,
38 } pmic;
39
get_rsb_rt_address(uint16_t hw_addr)40 static uint8_t get_rsb_rt_address(uint16_t hw_addr)
41 {
42 switch (hw_addr) {
43 case 0x3a3: return 0x2d;
44 case 0x745: return 0x3a;
45 }
46
47 return 0;
48 }
49
axp_read(uint8_t reg)50 int axp_read(uint8_t reg)
51 {
52 uint8_t val = 0;
53 int ret;
54
55 if (is_using_rsb()) {
56 return rsb_read(rsb_rt_addr, reg);
57 }
58
59 ret = i2c_write(pmic_bus_addr, 0, 0, ®, 1);
60 if (ret == 0) {
61 ret = i2c_read(pmic_bus_addr, 0, 0, &val, 1);
62 }
63 if (ret) {
64 ERROR("PMIC: Cannot read PMIC register %02x\n", reg);
65 return ret;
66 }
67
68 return val;
69 }
70
axp_write(uint8_t reg,uint8_t val)71 int axp_write(uint8_t reg, uint8_t val)
72 {
73 int ret;
74
75 if (is_using_rsb()) {
76 return rsb_write(rsb_rt_addr, reg, val);
77 }
78
79 ret = i2c_write(pmic_bus_addr, reg, 1, &val, 1);
80 if (ret) {
81 ERROR("PMIC: Cannot write PMIC register %02x\n", reg);
82 }
83
84 return ret;
85 }
86
rsb_init(int rsb_hw_addr)87 static int rsb_init(int rsb_hw_addr)
88 {
89 int ret;
90
91 ret = rsb_init_controller();
92 if (ret) {
93 return ret;
94 }
95
96 /* Switch to the recommended 3 MHz bus clock. */
97 ret = rsb_set_bus_speed(SUNXI_OSC24M_CLK_IN_HZ, 3000000);
98 if (ret) {
99 return ret;
100 }
101
102 /* Initiate an I2C transaction to switch the PMIC to RSB mode. */
103 ret = rsb_set_device_mode(AXP20X_MODE_RSB << 16 | AXP20X_MODE_REG << 8);
104 if (ret) {
105 return ret;
106 }
107
108 /* Associate the 8-bit runtime address with the 12-bit bus address. */
109 ret = rsb_assign_runtime_address(rsb_hw_addr, rsb_rt_addr);
110 if (ret) {
111 return ret;
112 }
113
114 return 0;
115 }
116
pmic_bus_init(uint16_t socid,uint16_t rsb_hw_addr)117 static int pmic_bus_init(uint16_t socid, uint16_t rsb_hw_addr)
118 {
119 int ret;
120
121 ret = sunxi_init_platform_r_twi(socid, is_using_rsb());
122 if (ret) {
123 INFO("Could not init platform bus: %d\n", ret);
124 pmic = UNKNOWN;
125 return ret;
126 }
127
128 if (is_using_rsb()) {
129 ret = rsb_init(rsb_hw_addr);
130 if (ret) {
131 pmic = UNKNOWN;
132 return ret;
133 }
134 } else {
135 /* initialise mi2cv driver */
136 i2c_init((void *)SUNXI_R_I2C_BASE);
137 }
138
139 return 0;
140 }
141
sunxi_pmic_setup(uint16_t socid,const void * fdt)142 int sunxi_pmic_setup(uint16_t socid, const void *fdt)
143 {
144 int node, parent, ret;
145 uint32_t reg;
146
147 if (fdt == NULL) {
148 INFO("No DTB, skipping PMIC detection and setup\n");
149 return -ENOENT;
150 }
151
152 node = fdt_node_offset_by_compatible(fdt, 0, "x-powers,axp806");
153 if (node >= 0) {
154 pmic = AXP305;
155 }
156
157 if (pmic == UNKNOWN) {
158 node = fdt_node_offset_by_compatible(fdt, 0, "x-powers,axp313a");
159 if (node >= 0) {
160 pmic = AXP313;
161 }
162 }
163
164 if (pmic == UNKNOWN) {
165 node = fdt_node_offset_by_compatible(fdt, 0, "x-powers,axp717");
166 if (node >= 0) {
167 pmic = AXP717;
168 }
169 }
170
171 if (pmic == UNKNOWN) {
172 INFO("PMIC: No known PMIC in DT, skipping setup.\n");
173 return -ENODEV;
174 }
175
176 if (fdt_read_uint32(fdt, node, "reg", ®)) {
177 ERROR("PMIC: PMIC DT node does not contain reg property.\n");
178 return -EINVAL;
179 }
180
181 pmic_bus_addr = reg;
182 parent = fdt_parent_offset(fdt, node);
183 ret = fdt_node_check_compatible(fdt, parent, "allwinner,sun8i-a23-rsb");
184 if (ret == 0) {
185 rsb_rt_addr = get_rsb_rt_address(pmic_bus_addr);
186 if (rsb_rt_addr == 0) {
187 ERROR("PMIC: no mapping for RSB address 0x%x\n",
188 pmic_bus_addr);
189 return -EINVAL;
190 }
191 }
192
193 INFO("Probing for PMIC on %s:\n", is_using_rsb() ? "RSB" : "I2C");
194
195 ret = pmic_bus_init(socid, pmic_bus_addr);
196 if (ret) {
197 return ret;
198 }
199
200 ret = axp_read(0x03);
201 switch (ret & 0xcf) {
202 case 0x40: /* AXP305 */
203 if (pmic == AXP305) {
204 INFO("PMIC: found AXP305, setting up regulators\n");
205 axp_setup_regulators(fdt);
206 } else {
207 pmic = UNKNOWN;
208 }
209 break;
210 case 0x48: /* AXP1530 */
211 case 0x4b: /* AXP313A */
212 case 0x4c: /* AXP313B */
213 if (pmic == AXP313) {
214 INFO("PMIC: found AXP313\n");
215 /* no regulators to set up */
216 } else {
217 pmic = UNKNOWN;
218 }
219 break;
220 case 0xcf: /* version reg not implemented on AXP717 */
221 if (pmic == AXP717) {
222 INFO("PMIC: found AXP717\n");
223 /* no regulators to set up, U-Boot takes care of this */
224 } else {
225 pmic = UNKNOWN;
226 }
227 break;
228 }
229
230 if (is_using_rsb()) {
231 /* Switch the PMIC back to I2C mode. */
232 return rsb_write(rsb_rt_addr, AXP20X_MODE_REG, AXP20X_MODE_I2C);
233 }
234
235 if (pmic == UNKNOWN) {
236 INFO("Incompatible or unknown PMIC found.\n");
237 return -ENODEV;
238 }
239
240 return 0;
241 }
242
sunxi_power_down(void)243 void sunxi_power_down(void)
244 {
245 int ret;
246
247 if (pmic == UNKNOWN) {
248 return;
249 }
250
251 /* Re-initialise after rich OS might have used it. */
252 ret = pmic_bus_init(SUNXI_SOC_H616, pmic_bus_addr);
253 if (ret) {
254 return;
255 }
256
257 switch (pmic) {
258 case AXP305:
259 axp_setbits(0x32, BIT(7));
260 break;
261 case AXP313:
262 axp_setbits(0x1a, BIT(7));
263 break;
264 case AXP717:
265 axp_setbits(0x27, BIT(0));
266 break;
267 default:
268 break;
269 }
270 }
271
sunxi_cpu_power_off_self(void)272 void sunxi_cpu_power_off_self(void)
273 {
274 u_register_t mpidr = read_mpidr();
275 unsigned int core = MPIDR_AFFLVL0_VAL(mpidr);
276
277 /* Enable the CPUIDLE hardware (only really needs to be done once). */
278 mmio_write_32(SUNXI_CPUIDLE_EN_REG, 0x16aa0000);
279 mmio_write_32(SUNXI_CPUIDLE_EN_REG, 0xaa160001);
280
281 /* Trigger power off for this core. */
282 mmio_write_32(SUNXI_CORE_CLOSE_REG, BIT_32(core));
283 }
284