| /rk3399_ARM-atf/drivers/renesas/common/ddr/ddr_a/ |
| H A D | ddr_init_d3.c | 28 mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); in init_ddr_d3_1866()
29 mmio_write_32(DBSC_DBKIND, 0x00000007); in init_ddr_d3_1866()
30 mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a01); in init_ddr_d3_1866()
31 mmio_write_32(DBSC_DBPHYCONF0, 0x00000001); in init_ddr_d3_1866()
32 mmio_write_32(DBSC_DBTR0, 0x0000000D); in init_ddr_d3_1866()
33 mmio_write_32(DBSC_DBTR1, 0x00000009); in init_ddr_d3_1866()
34 mmio_write_32(DBSC_DBTR2, 0x00000000); in init_ddr_d3_1866()
35 mmio_write_32(DBSC_DBTR3, 0x0000000D); in init_ddr_d3_1866()
36 mmio_write_32(DBSC_DBTR4, 0x000D000D); in init_ddr_d3_1866()
37 mmio_write_32(DBSC_DBTR5, 0x0000002D); in init_ddr_d3_1866()
[all …]
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| H A D | ddr_init_e3.c | 64 mmio_write_32(CPG_CPGWPR, 0x5A5AFFFF); in init_ddr()
65 mmio_write_32(CPG_CPGWPCR, 0xA5A50000); in init_ddr()
67 mmio_write_32(CPG_SRCR4, 0x20000000); in init_ddr()
69 mmio_write_32(0xE61500DC, 0xe2200000); /* Change to 1584Mbps */ in init_ddr()
73 mmio_write_32(CPG_SRSTCLR4, 0x20000000); in init_ddr()
75 mmio_write_32(CPG_CPGWPCR, 0xA5A50001); in init_ddr()
78 mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); in init_ddr()
79 mmio_write_32(DBSC_DBKIND, 0x00000007); in init_ddr()
82 mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a02); /* 1GB */ in init_ddr()
84 mmio_write_32(DBSC_DBMEMCONF_0_0, 0x10030a02); /* 2GB(default) */ in init_ddr()
[all …]
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| H A D | ddr_init_v3m.c | 19 mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); in init_ddr_v3m_1600()
20 mmio_write_32(DBSC_DBKIND, 0x00000007); in init_ddr_v3m_1600()
22 mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a02); // 1GB: Eagle in init_ddr_v3m_1600()
24 mmio_write_32(DBSC_DBMEMCONF_0_0, 0x10030a02); // 2GB: V3MSK in init_ddr_v3m_1600()
26 mmio_write_32(DBSC_DBPHYCONF0, 0x00000001); in init_ddr_v3m_1600()
27 mmio_write_32(DBSC_DBTR0, 0x0000000B); in init_ddr_v3m_1600()
28 mmio_write_32(DBSC_DBTR1, 0x00000008); in init_ddr_v3m_1600()
29 mmio_write_32(DBSC_DBTR3, 0x0000000B); in init_ddr_v3m_1600()
30 mmio_write_32(DBSC_DBTR4, 0x000B000B); in init_ddr_v3m_1600()
31 mmio_write_32(DBSC_DBTR5, 0x00000027); in init_ddr_v3m_1600()
[all …]
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| /rk3399_ARM-atf/plat/nxp/common/soc_errata/ |
| H A D | errata_a050426.c | 26 mmio_write_32(0x700117E60, (val3 | 0x80000001)); in erratum_a050426()
28 mmio_write_32(0x700117E90, (val4 & 0xFFDFFFFF)); in erratum_a050426()
32 mmio_write_32(0x706312000 + (i * 4), 0x55555555); in erratum_a050426()
33 mmio_write_32(0x706312400 + (i * 4), 0x55555555); in erratum_a050426()
34 mmio_write_32(0x706312800 + (i * 4), 0x55555555); in erratum_a050426()
35 mmio_write_32(0x706314000 + (i * 4), 0x55555555); in erratum_a050426()
36 mmio_write_32(0x706314400 + (i * 4), 0x55555555); in erratum_a050426()
37 mmio_write_32(0x706314800 + (i * 4), 0x55555555); in erratum_a050426()
38 mmio_write_32(0x706314c00 + (i * 4), 0x55555555); in erratum_a050426()
41 mmio_write_32(0x706316000 + (i * 4), 0x55555555); in erratum_a050426()
[all …]
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| /rk3399_ARM-atf/plat/hisilicon/hikey/ |
| H A D | hikey_ddr.c | 26 mmio_write_32((0xf7032000 + 0x000), data); in init_pll()
34 mmio_write_32((0xf7800000 + 0x000), data); in init_pll()
40 mmio_write_32(PERI_SC_PERIPH_CTRL14, 0x2101); in init_pll()
44 mmio_write_32(PERI_SC_PERIPH_CTRL14, 0x2001); in init_pll()
48 mmio_write_32(PERI_SC_PERIPH_CTRL14, 0x2201); in init_pll()
52 mmio_write_32(0xf7032000 + 0x02c, 0x5110103e); in init_pll()
58 mmio_write_32(0xf7032000 + 0x050, data); in init_pll()
62 mmio_write_32(PERI_SC_PERIPH_CTRL14, 0x2101); in init_pll()
66 mmio_write_32(PERI_SC_PERIPH_CTRL14, 0x2001); in init_pll()
70 mmio_write_32(PERI_SC_PERIPH_CTRL14, 0x2201); in init_pll()
[all …]
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| /rk3399_ARM-atf/plat/hisilicon/hikey960/ |
| H A D | hikey960_bl_common.c | 18 mmio_write_32(0xfff350b4, 0xf0002000); in hikey960_clk_init()
20 mmio_write_32(0xfff350bc, 0xfc004c00); in hikey960_clk_init()
32 mmio_write_32(PMC_PPLL3_CTRL0_REG, 0x4904305); in hikey960_enable_ppll3()
33 mmio_write_32(PMC_PPLL3_CTRL1_REG, 0x2300000); in hikey960_enable_ppll3()
34 mmio_write_32(PMC_PPLL3_CTRL1_REG, 0x6300000); in hikey960_enable_ppll3()
44 mmio_write_32(PMC_NOC_POWER_IDLEREQ_REG, pmc_value); in bus_idle_clear()
63 mmio_write_32(CRG_CLKDIV20_REG, 0x00020002); in set_vivobus_power_up()
64 mmio_write_32(CRG_PEREN0_REG, 0x00001000); in set_vivobus_power_up()
70 mmio_write_32(CRG_CLKDIV5_REG, 0x003f000b); in set_dss_power_up()
72 mmio_write_32(CRG_CLKDIV3_REG, 0xf0001000); in set_dss_power_up()
[all …]
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| /rk3399_ARM-atf/plat/intel/soc/common/soc/ |
| H A D | socfpga_firewall.c | 22 mmio_write_32(SOCFPGA_L4_PER_SCR(NAND_REGISTER), DISABLE_L4_FIREWALL); in enable_ns_peripheral_access()
26 mmio_write_32(SOCFPGA_L4_PER_SCR(NAND_DATA), DISABLE_L4_FIREWALL); in enable_ns_peripheral_access()
29 mmio_write_32(SOCFPGA_L4_SYS_SCR(NAND_ECC), DISABLE_L4_FIREWALL); in enable_ns_peripheral_access()
30 mmio_write_32(SOCFPGA_L4_SYS_SCR(NAND_READ_ECC), DISABLE_L4_FIREWALL); in enable_ns_peripheral_access()
31 mmio_write_32(SOCFPGA_L4_SYS_SCR(NAND_WRITE_ECC), in enable_ns_peripheral_access()
34 mmio_write_32(SOCFPGA_L4_PER_SCR(USB0_REGISTER), DISABLE_L4_FIREWALL); in enable_ns_peripheral_access()
35 mmio_write_32(SOCFPGA_L4_PER_SCR(USB1_REGISTER), DISABLE_L4_FIREWALL); in enable_ns_peripheral_access()
36 mmio_write_32(SOCFPGA_L4_SYS_SCR(USB0_ECC), DISABLE_L4_FIREWALL); in enable_ns_peripheral_access()
37 mmio_write_32(SOCFPGA_L4_SYS_SCR(USB1_ECC), DISABLE_L4_FIREWALL); in enable_ns_peripheral_access()
39 mmio_write_32(SOCFPGA_L4_PER_SCR(SPI_MASTER0), DISABLE_L4_FIREWALL); in enable_ns_peripheral_access()
[all …]
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| /rk3399_ARM-atf/plat/imx/imx8m/ddr/ |
| H A D | dram_retention.c | 36 mmio_write_32(DDRC_DRAMTMG2(0) + offset, dram_info.rank_setting[i][0]); in rank_setting_update()
38 mmio_write_32(DDRC_DRAMTMG9(0) + offset, dram_info.rank_setting[i][1]); in rank_setting_update()
42 mmio_write_32(DDRC_RANKCTL(0) + offset, in rank_setting_update()
47 mmio_write_32(DDRC_RANKCTL(0), dram_info.rank_setting[0][2]); in rank_setting_update()
59 mmio_write_32(DDRC_PCTRL_0(0), 0x0); in dram_enter_retention()
66 mmio_write_32(DDRC_PWRCTL(0), 0xaa); in dram_enter_retention()
79 mmio_write_32(DDRC_DFIMISC(0), 0x0); in dram_enter_retention()
80 mmio_write_32(DDRC_SWCTL(0), 0x0); in dram_enter_retention()
81 mmio_write_32(DDRC_DFIMISC(0), 0x1f00); in dram_enter_retention()
82 mmio_write_32(DDRC_DFIMISC(0), 0x1f20); in dram_enter_retention()
[all …]
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| H A D | clock.c | 24 mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(0), (0x7 << 24) | (0x7 << 16)); in ddr_pll_bypass_100mts()
25 mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_SET(0), (0x2 << 24)); in ddr_pll_bypass_100mts()
28 mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1), (0x7 << 24) | (0x7 << 16)); in ddr_pll_bypass_100mts()
29 mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1), (0x2 << 24) | (0x1 << 16)); in ddr_pll_bypass_100mts()
32 mmio_write_32(DRAM_SEL_CFG + 0x4, BIT(24)); in ddr_pll_bypass_100mts()
38 mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(0), (0x7 << 24) | (0x7 << 16)); in ddr_pll_bypass_400mts()
39 mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_SET(0), (0x1 << 24) | (0x1 << 16)); in ddr_pll_bypass_400mts()
42 mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1), (0x7 << 24) | (0x7 << 16)); in ddr_pll_bypass_400mts()
43 mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1), (0x3 << 24) | (0x1 << 16)); in ddr_pll_bypass_400mts()
46 mmio_write_32(DRAM_SEL_CFG + 0x4, BIT(24)); in ddr_pll_bypass_400mts()
[all …]
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| /rk3399_ARM-atf/plat/mediatek/mt8183/drivers/emi_mpu/ |
| H A D | emi_mpu.c | 52 mmio_write_32(EMI_MPU_APC0, 0); in emi_mpu_set_region_protection()
53 mmio_write_32(EMI_MPU_SA0, start); in emi_mpu_set_region_protection()
54 mmio_write_32(EMI_MPU_EA0, end); in emi_mpu_set_region_protection()
55 mmio_write_32(EMI_MPU_APC0, access_permission); in emi_mpu_set_region_protection()
59 mmio_write_32(EMI_MPU_APC1, 0); in emi_mpu_set_region_protection()
60 mmio_write_32(EMI_MPU_SA1, start); in emi_mpu_set_region_protection()
61 mmio_write_32(EMI_MPU_EA1, end); in emi_mpu_set_region_protection()
62 mmio_write_32(EMI_MPU_APC1, access_permission); in emi_mpu_set_region_protection()
66 mmio_write_32(EMI_MPU_APC2, 0); in emi_mpu_set_region_protection()
67 mmio_write_32(EMI_MPU_SA2, start); in emi_mpu_set_region_protection()
[all …]
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| /rk3399_ARM-atf/drivers/renesas/rzg/qos/G2M/ |
| H A D | qos_init_g2m_v10.c | 75 mmio_write_32(AXI_ADSPLCR0, 0x00000000U); in qos_init_g2m_v10()
76 mmio_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT | in qos_init_g2m_v10()
79 mmio_write_32(AXI_ADSPLCR2, 0x089A0000U); in qos_init_g2m_v10()
80 mmio_write_32(AXI_ADSPLCR3, 0x00000000U); in qos_init_g2m_v10()
91 mmio_write_32(QOSCTRL_RAS, 0x00000028U); in qos_init_g2m_v10()
92 mmio_write_32(QOSCTRL_FIXTH, 0x000F0005U); in qos_init_g2m_v10()
93 mmio_write_32(QOSCTRL_REGGD, 0x00000000U); in qos_init_g2m_v10()
95 mmio_write_32(QOSCTRL_DANT, 0x00100804U); in qos_init_g2m_v10()
96 mmio_write_32(QOSCTRL_EC, 0x00000000U); in qos_init_g2m_v10()
98 mmio_write_32(QOSCTRL_FSS, 0x000003e8U); in qos_init_g2m_v10()
[all …]
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| H A D | qos_init_g2m_v11.c | 119 mmio_write_32(AXI_ADSPLCR0, 0x00000000U); in qos_init_g2m_v11()
120 mmio_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT | in qos_init_g2m_v11()
123 mmio_write_32(AXI_ADSPLCR2, 0x00001004U); in qos_init_g2m_v11()
124 mmio_write_32(AXI_ADSPLCR3, 0x00000000U); in qos_init_g2m_v11()
144 mmio_write_32(QOSCTRL_RAS, 0x00000044U); in qos_init_g2m_v11()
146 mmio_write_32(QOSCTRL_DANT, 0x0020100AU); in qos_init_g2m_v11()
147 mmio_write_32(QOSCTRL_INSFC, 0x06330001U); in qos_init_g2m_v11()
148 mmio_write_32(QOSCTRL_RACNT0, 0x02010003U); /* GPU Boost Mode ON */ in qos_init_g2m_v11()
150 mmio_write_32(QOSCTRL_SL_INIT, in qos_init_g2m_v11()
154 mmio_write_32(QOSCTRL_REF_ARS, in qos_init_g2m_v11()
[all …]
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| /rk3399_ARM-atf/plat/rockchip/rk3288/drivers/secure/ |
| H A D | secure.c | 21 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(21), in sgrf_ddr_rgn_global_bypass()
25 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(21), in sgrf_ddr_rgn_global_bypass()
66 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6 + (rgn * 2)), in sgrf_ddr_rgn_config()
70 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6 + (rgn * 2) + 1), in sgrf_ddr_rgn_config()
74 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6 + (rgn * 2)), in sgrf_ddr_rgn_config()
78 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6 + (rgn * 2)), in sgrf_ddr_rgn_config()
84 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(0), SGRF_PCLK_WDT_GATE); in secure_watchdog_gate()
89 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(0), SGRF_PCLK_WDT_UNGATE); in secure_watchdog_ungate()
94 mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, 0); in sram_secure_timer_init()
96 mmio_write_32(STIMER1_BASE + TIMER_LOAD_COUNT0, 0xffffffff); in sram_secure_timer_init()
[all …]
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| /rk3399_ARM-atf/plat/mediatek/mt8173/drivers/spm/ |
| H A D | spm.c | 96 mmio_write_32(SPM_POWERON_CONFIG_SET, SPM_REGWR_CFG_KEY | SPM_REGWR_EN); in spm_register_init()
98 mmio_write_32(SPM_POWER_ON_VAL0, 0); in spm_register_init()
99 mmio_write_32(SPM_POWER_ON_VAL1, POWER_ON_VAL1_DEF); in spm_register_init()
100 mmio_write_32(SPM_PCM_PWR_IO_EN, 0); in spm_register_init()
102 mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_PCM_SW_RESET); in spm_register_init()
103 mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY); in spm_register_init()
107 mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_IM_SLEEP_DVS); in spm_register_init()
108 mmio_write_32(SPM_PCM_CON1, CON1_CFG_KEY | CON1_EVENT_LOCK_EN | in spm_register_init()
110 mmio_write_32(SPM_PCM_IM_PTR, 0); in spm_register_init()
111 mmio_write_32(SPM_PCM_IM_LEN, 0); in spm_register_init()
[all …]
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| H A D | spm_mcdi.c | 248 mmio_write_32(SPM_PCM_REG_DATA_INI, PCM_MCDI_HANDSHAKE_SYNC); in spm_mcdi_cpu_wake_up_event()
249 mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R6); in spm_mcdi_cpu_wake_up_event()
250 mmio_write_32(SPM_PCM_PWR_IO_EN, 0); in spm_mcdi_cpu_wake_up_event()
269 mmio_write_32(SPM_SLEEP_CPU_WAKEUP_EVENT, wake_up_event); in spm_mcdi_cpu_wake_up_event()
275 mmio_write_32(SPM_PCM_REG_DATA_INI, PCM_MCDI_UPDATE_INFORM); in spm_mcdi_cpu_wake_up_event()
276 mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R6); in spm_mcdi_cpu_wake_up_event()
277 mmio_write_32(SPM_PCM_PWR_IO_EN, 0); in spm_mcdi_cpu_wake_up_event()
283 mmio_write_32(SPM_PCM_REG_DATA_INI, 0x0); in spm_mcdi_cpu_wake_up_event()
284 mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R6); in spm_mcdi_cpu_wake_up_event()
285 mmio_write_32(SPM_PCM_PWR_IO_EN, 0); in spm_mcdi_cpu_wake_up_event()
[all …]
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| /rk3399_ARM-atf/plat/rockchip/rk3588/drivers/secure/ |
| H A D | secure.c | 20 mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_MST(1), 0x0000ffff); in secure_fw_master_init()
22 mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_MST(14), 0x00000000); in secure_fw_master_init()
26 mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_MST(36), 0xffff0000); in secure_fw_master_init()
33 mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_MST(i), 0xffffffff); in secure_fw_master_init()
37 mmio_write_32(FIREWALL_SYSMEM_BASE + FIREWALL_SYSMEM_MST(19), 0x000000ff); in secure_fw_master_init()
39 mmio_write_32(FIREWALL_SYSMEM_BASE + FIREWALL_SYSMEM_MST(38), 0x000000ff); in secure_fw_master_init()
41 mmio_write_32(FIREWALL_SYSMEM_BASE + FIREWALL_SYSMEM_MST(41), 0x00000000); in secure_fw_master_init()
48 mmio_write_32(FIREWALL_SYSMEM_BASE + FIREWALL_SYSMEM_MST(i), in secure_fw_master_init()
53 mmio_write_32(FIREWALL_DSU_BASE + FIREWALL_DSU_MST(0), 0xffffffff); in secure_fw_master_init()
54 mmio_write_32(FIREWALL_DSU_BASE + FIREWALL_DSU_MST(1), 0x00000000); in secure_fw_master_init()
[all …]
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| /rk3399_ARM-atf/plat/rockchip/rk3399/drivers/secure/ |
| H A D | secure.c | 21 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), in sgrf_ddr_rgn_global_bypass()
25 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), in sgrf_ddr_rgn_global_bypass()
74 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(rgn), in sgrf_ddr_rgn_config()
78 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(rgn + 8), in sgrf_ddr_rgn_config()
81 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), in sgrf_ddr_rgn_config()
92 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), in secure_watchdog_gate()
104 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), in secure_watchdog_ungate()
111 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT0, 0xffffffff); in sram_secure_timer_init()
112 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT1, 0xffffffff); in sram_secure_timer_init()
114 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0); in sram_secure_timer_init()
[all …]
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| /rk3399_ARM-atf/plat/rockchip/rk3576/drivers/pmu/ |
| H A D | pmu.c | 94 mmio_write_32(PMU_BASE + PMU2_CPU_PWR_SFTCON(cpu), in cpu_power_domain_ctr()
150 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), in cpus_power_domain_on()
163 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), in cpus_power_domain_on()
183 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), in cpus_power_domain_off()
197 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), in cpus_power_domain_off()
233 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), in rockchip_soc_cores_pwr_dm_on_finish()
259 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), in rockchip_soc_cores_pwr_dm_resume()
289 mmio_write_32(CCI_GRF_BASE + CCIGRF_CON(4), 0xffffffff); in ddr_resume()
290 mmio_write_32(LITCORE_GRF_BASE + COREGRF_CPU_CON(1), in ddr_resume()
298 mmio_write_32(SYS_SGRF_BASE + SYSSGRF_SOC_CON(19), 0x00070000); in ddr_resume()
[all …]
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| /rk3399_ARM-atf/plat/intel/soc/stratix10/soc/ |
| H A D | s10_clock_manager.c | 43 mmio_write_32(ALT_CLKMGR_MAINPLL + in config_clkmgr_handoff()
48 mmio_write_32(ALT_CLKMGR_PERPLL + in config_clkmgr_handoff()
60 mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_PLLGLOB, in config_clkmgr_handoff()
62 mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_FDBCK, in config_clkmgr_handoff()
64 mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_VCOCALIB, in config_clkmgr_handoff()
67 mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_PLLC0, in config_clkmgr_handoff()
69 mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_PLLC1, in config_clkmgr_handoff()
72 mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_NOCDIV, in config_clkmgr_handoff()
82 mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_PLLGLOB, in config_clkmgr_handoff()
84 mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_FDBCK, in config_clkmgr_handoff()
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| /rk3399_ARM-atf/plat/rockchip/rk3568/drivers/soc/ |
| H A D | soc.c | 39 mmio_write_32(STIMER0_CHN_BASE(1) + TIMER_CONTROL_REG, TIMER_DIS); in secure_timer_init()
40 mmio_write_32(STIMER0_CHN_BASE(1) + TIMER_LOAD_COUNT0, 0xffffffff); in secure_timer_init()
41 mmio_write_32(STIMER0_CHN_BASE(1) + TIMER_LOAD_COUNT1, 0xffffffff); in secure_timer_init()
44 mmio_write_32(STIMER0_CHN_BASE(1) + TIMER_CONTROL_REG, TIMER_EN); in secure_timer_init()
49 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(0), 0xffff0000); in sgrf_init()
50 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(1), 0xffff0000); in sgrf_init()
51 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(2), 0xffff0000); in sgrf_init()
52 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(3), 0xffff0000); in sgrf_init()
53 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(4), 0xffff0000); in sgrf_init()
54 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(5), 0xffff0000); in sgrf_init()
[all …]
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| /rk3399_ARM-atf/plat/rockchip/rk3568/drivers/pmu/ |
| H A D | pmu.c | 62 mmio_write_32(PMUGRF_BASE + PMU_GRF_SOC_CON(0), WRITE_MASK_SET(BIT(7))); in pmu_pmic_sleep_mode_config()
63 mmio_write_32(PMUGRF_BASE + PMU_GRF_GPIO0A_IOMUX_L, PMIC_SLEEP_FUN); in pmu_pmic_sleep_mode_config()
69 mmio_write_32(PMU_BASE + PMU_WAKEUP_INT_CON, WRITE_MASK_SET(BIT(WAKEUP_GPIO0_INT_EN))); in pmu_wakeup_source_config()
88 mmio_write_32(PMU_BASE + PMU_PLLPD_CON, WRITE_MASK_SET(pll_id)); in pmu_pll_powerdown_config()
95 mmio_write_32(PMU_BASE + PMU_DSU_STABLE_CNT, 0x180); in pmu_stable_count_config()
96 mmio_write_32(PMU_BASE + PMU_PMIC_STABLE_CNT, 0x180); in pmu_stable_count_config()
97 mmio_write_32(PMU_BASE + PMU_OSC_STABLE_CNT, 0x180); in pmu_stable_count_config()
98 mmio_write_32(PMU_BASE + PMU_WAKEUP_RSTCLR_CNT, 0x180); in pmu_stable_count_config()
99 mmio_write_32(PMU_BASE + PMU_PLL_LOCK_CNT, 0x180); in pmu_stable_count_config()
100 mmio_write_32(PMU_BASE + PMU_DSU_PWRUP_CNT, 0x180); in pmu_stable_count_config()
[all …]
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| /rk3399_ARM-atf/plat/mediatek/drivers/dfd/mt8188/ |
| H A D | plat_dfd.c | 19 mmio_write_32(MTK_DRM_LATCH_CTL1, MTK_DRM_LATCH_CTL1_VAL); in dfd_setup()
20 mmio_write_32(MTK_DRM_LATCH_CTL2, MTK_DRM_LATCH_CTL2_VAL); in dfd_setup()
21 mmio_write_32(MTK_WDT_LATCH_CTL2, MTK_WDT_LATCH_CTL2_VAL); in dfd_setup()
31 mmio_write_32(DFD_INTERNAL_PWR_ON, 0xB); in dfd_setup()
32 mmio_write_32(DFD_CHAIN_LENGTH0, chain_length); in dfd_setup()
33 mmio_write_32(DFD_INTERNAL_SHIFT_CLK_RATIO, 0x0); in dfd_setup()
34 mmio_write_32(DFD_INTERNAL_TEST_SO_OVER_64, 0x1); in dfd_setup()
36 mmio_write_32(DFD_TEST_SI_0, 0x0); in dfd_setup()
37 mmio_write_32(DFD_TEST_SI_1, 0x0); in dfd_setup()
38 mmio_write_32(DFD_TEST_SI_2, 0x0); in dfd_setup()
[all …]
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| /rk3399_ARM-atf/plat/rockchip/rk3568/drivers/otp/ |
| H A D | otp.c | 41 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(26), in enable_otp_clk()
48 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(26), in enable_otp_clk()
55 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(26), in enable_otp_clk()
62 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(34), in enable_otp_clk()
69 mmio_write_32(SCRU_BASE + SCRU_GATE_CON01, in enable_otp_clk()
76 mmio_write_32(SCRU_BASE + SCRU_GATE_CON01, in enable_otp_clk()
83 mmio_write_32(SCRU_BASE + SCRU_GATE_CON01, in enable_otp_clk()
99 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(26), in restore_otp_clk()
104 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(26), in restore_otp_clk()
109 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(26), in restore_otp_clk()
[all …]
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| /rk3399_ARM-atf/drivers/renesas/rzg/qos/G2H/ |
| H A D | qos_init_g2h_v30.c | 119 mmio_write_32(AXI_ADSPLCR0, ADSPLCR0_AREA(split_area)); in qos_init_g2h_v30()
120 mmio_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT | in qos_init_g2h_v30()
123 mmio_write_32(AXI_ADSPLCR2, 0x00001004U); in qos_init_g2h_v30()
124 mmio_write_32(AXI_ADSPLCR3, 0x00000000U); in qos_init_g2h_v30()
126 mmio_write_32(AXI_ADSPLCR0, ADSPLCR0_AREA(split_area)); in qos_init_g2h_v30()
145 mmio_write_32(QOSCTRL_RAS, 0x00000044U); in qos_init_g2h_v30()
147 mmio_write_32(QOSCTRL_DANT, 0x0020100AU); in qos_init_g2h_v30()
148 mmio_write_32(QOSCTRL_FSS, 0x0000000AU); in qos_init_g2h_v30()
149 mmio_write_32(QOSCTRL_INSFC, 0x06330001U); in qos_init_g2h_v30()
150 mmio_write_32(QOSCTRL_RACNT0, 0x00010003U); in qos_init_g2h_v30()
[all …]
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| /rk3399_ARM-atf/plat/mediatek/mt8195/drivers/dfd/ |
| H A D | plat_dfd.c | 20 mmio_write_32(MTK_WDT_LATCH_CTL2, MTK_WDT_LATCH_CTL2_VAL); in dfd_setup()
21 mmio_write_32(MTK_WDT_INTERVAL, MTK_WDT_INTERVAL_VAL); in dfd_setup()
22 mmio_write_32(MTK_DRM_LATCH_CTL2, MTK_DRM_LATCH_CTL2_VAL); in dfd_setup()
23 mmio_write_32(MTK_DRM_LATCH_CTL1, MTK_DRM_LATCH_CTL1_VAL); in dfd_setup()
62 mmio_write_32(DFD_INTERNAL_PWR_ON, 0xB); in dfd_setup()
65 mmio_write_32(DFD_CHAIN_LENGTH0, chain_length); in dfd_setup()
68 mmio_write_32(DFD_INTERNAL_SHIFT_CLK_RATIO, 0x0); in dfd_setup()
71 mmio_write_32(DFD_INTERNAL_TEST_SO_OVER_64, 0x1); in dfd_setup()
74 mmio_write_32(DFD_TEST_SI_0, 0x0); in dfd_setup()
75 mmio_write_32(DFD_TEST_SI_1, 0x0); in dfd_setup()
[all …]
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