| #
940c1e64 |
| 11-Dec-2023 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes If2743827,I163f8169,I97a69650 into integration
* changes:
feat(imx8m): add 3600 MTps DDR PLL rate
fix(imx8m): align 3200 MTps rate with U-Boot
fix(imx8m): handle 3734 in addition
Merge changes If2743827,I163f8169,I97a69650 into integration
* changes:
feat(imx8m): add 3600 MTps DDR PLL rate
fix(imx8m): align 3200 MTps rate with U-Boot
fix(imx8m): handle 3734 in addition to 3733 and 3732 MTps rates
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| #
f1bb459c |
| 30-Nov-2023 |
Marek Vasut <marex@denx.de> |
feat(imx8m): add 3600 MTps DDR PLL rate
Add 3600 MTps DRAM and its 900 MHz PLL setting M=300 P=8 S=0 , so
24 MHz * 300 / 8 / 2^0 = 900 MHz ~ 3600 MTps (x4) .
Signed-off-by: Marek Vasut <marex@denx.
feat(imx8m): add 3600 MTps DDR PLL rate
Add 3600 MTps DRAM and its 900 MHz PLL setting M=300 P=8 S=0 , so
24 MHz * 300 / 8 / 2^0 = 900 MHz ~ 3600 MTps (x4) .
Signed-off-by: Marek Vasut <marex@denx.de>
Change-Id: If2743827294efc0f981718f04b772cc462846195
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| #
060fe633 |
| 30-Nov-2023 |
Marek Vasut <marex@denx.de> |
fix(imx8m): align 3200 MTps rate with U-Boot
The 3200 MTps DRAM and its 800 MHz PLL setting in U-Boot is set to
M=300 P=9 S=0 , so 24 MHz * 300 / 9 / 2^0 = 800 MHz ~ 3200 MTps (x4) .
Make sure the P
fix(imx8m): align 3200 MTps rate with U-Boot
The 3200 MTps DRAM and its 800 MHz PLL setting in U-Boot is set to
M=300 P=9 S=0 , so 24 MHz * 300 / 9 / 2^0 = 800 MHz ~ 3200 MTps (x4) .
Make sure the PLL settings are aligned across software components.
Signed-off-by: Marek Vasut <marex@denx.de>
Change-Id: I163f81696be213acf6ecebe89ff2c76d41484cc5
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| #
cb60a876 |
| 30-Nov-2023 |
Marek Vasut <marex@denx.de> |
fix(imx8m): handle 3734 in addition to 3733 and 3732 MTps rates
The new MX8M DDR tool 3.31 now generates a programming file which uses
data rate 3734 instead of 3733 or 3732 . Handle another roundin
fix(imx8m): handle 3734 in addition to 3733 and 3732 MTps rates
The new MX8M DDR tool 3.31 now generates a programming file which uses
data rate 3734 instead of 3733 or 3732 . Handle another rounding option .
Signed-off-by: Marek Vasut <marex@denx.de>
Change-Id: I97a69650c12d78dfff9dcdb23e27fd6590f57fc0
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| #
b8f365c3 |
| 06-Sep-2023 |
Yann Gautier <yann.gautier@st.com> |
Merge "feat(imx8m): add more dram pll setting" into integration
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| #
89474044 |
| 31-Aug-2023 |
Marek Vasut <marex@denx.de> |
feat(imx8m): add more dram pll setting
Add DRAM PLL frequency setting for 3732mts & 3733mts.
Change-Id: I74feab2185376bbb84826d7ee79b5e25cbc4d263
Signed-off-by: Marek Vasut <marex@denx.de>
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| #
5864b58a |
| 09-Mar-2023 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "imx8m_misc_changes" into integration
* changes:
feat(imx8mq): enable dram dvfs support on imx8mq
feat(imx8m): use non-fast wakeup stop mode for system suspend
feat(im
Merge changes from topic "imx8m_misc_changes" into integration
* changes:
feat(imx8mq): enable dram dvfs support on imx8mq
feat(imx8m): use non-fast wakeup stop mode for system suspend
feat(imx8mq): correct the slot ack setting for STOP mode
feat(imx8mq): add anamix pll override setting for DSM mode
feat(imx8mq): add workaround code for ERR11171 on imx8mq
feat(imx8mq): add the dram retention support for imx8mq
feat(imx8mq): add version for B2
fix(imx8m): backup mr12/14 value from lpddr4 chip
fix(imx8m): add ddr4 dvfs sw workaround for ERR050712
fix(imx8m): fix coverity out of bound access issue
fix(imx8m): fix the dram retention random hang on some imx8mq Rev2.0
feat(imx8m): add more dram pll setting
fix(imx8m): fix the current fsp init
fix(imx8m): fix the rank to rank space issue
fix(imx8m): fix the dfiphymaster setting after dvfs
feat(imx8m): update the ddr4 dvfs flow to include ddr3l support
fix(imx8m): correct the rank info get fro mstr
feat(imx8m): fix the ddr4 dvfs random hang on imx8m
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| #
8962bdd6 |
| 14-Jan-2020 |
Jacky Bai <ping.bai@nxp.com> |
feat(imx8mq): enable dram dvfs support on imx8mq
Enable DRAM DVFS support on i.MX8MQ.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Id72c5eb9625936052ec51e5a52d9d31175ed1b1b
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| #
4234b902 |
| 19-Oct-2020 |
Jacky Bai <ping.bai@nxp.com> |
feat(imx8m): add more dram pll setting
Add DRAM PLL frequency setting for 3200mts & 4000mts.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Change-Id: I4
feat(imx8m): add more dram pll setting
Add DRAM PLL frequency setting for 3200mts & 4000mts.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Change-Id: I4b0609f9e7c0f35d75a26ec9ccebec77b3dbe68f
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| #
0cb8dd7a |
| 08-Jul-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes Iec22dcab,Ib88b4b5d,I50cd6b82,If1167785,I9b3a08ef, ... into integration
* changes:
feat(imx8m): keep pu domains in default state during boot stage
feat(imx8m): add the PU power dom
Merge changes Iec22dcab,Ib88b4b5d,I50cd6b82,If1167785,I9b3a08ef, ... into integration
* changes:
feat(imx8m): keep pu domains in default state during boot stage
feat(imx8m): add the PU power domain support on imx8mm/mn
feat(imx8m): add the anamix pll override setting
feat(imx8m): add the ddr frequency change support for imx8m family
feat(imx8mn): enable dram retention suuport on imx8mn
feat(imx8mm): enable dram retention suuport on imx8mm
feat(imx8m): add dram retention flow for imx8m family
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| #
9c336f61 |
| 25-Nov-2019 |
Jacky Bai <ping.bai@nxp.com> |
feat(imx8m): add the ddr frequency change support for imx8m family
Add the DDR frequency change support.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: If1167785796b8678c351569b83d2922c66f6
feat(imx8m): add the ddr frequency change support for imx8m family
Add the DDR frequency change support.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: If1167785796b8678c351569b83d2922c66f6e530
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