39 	mmio_write_32(STIMER0_CHN_BASE(1) + TIMER_CONTROL_REG, TIMER_DIS);  in secure_timer_init()
40 	mmio_write_32(STIMER0_CHN_BASE(1) + TIMER_LOAD_COUNT0, 0xffffffff);  in secure_timer_init()
41 	mmio_write_32(STIMER0_CHN_BASE(1) + TIMER_LOAD_COUNT1, 0xffffffff);  in secure_timer_init()
44 	mmio_write_32(STIMER0_CHN_BASE(1) + TIMER_CONTROL_REG, TIMER_EN);  in secure_timer_init()
49 	mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(0), 0xffff0000);  in sgrf_init()
50 	mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(1), 0xffff0000);  in sgrf_init()
51 	mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(2), 0xffff0000);  in sgrf_init()
52 	mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(3), 0xffff0000);  in sgrf_init()
53 	mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(4), 0xffff0000);  in sgrf_init()
54 	mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(5), 0xffff0000);  in sgrf_init()
55 	mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(6), 0xffff0000);  in sgrf_init()
56 	mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(7), 0xffff0000);  in sgrf_init()
57 	mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(8), 0xffff0000);  in sgrf_init()
59 	mmio_write_32(DDRSGRF_BASE + FIREWALL_DDR_FW_DDR_CON_REG, 0xffff0000);  in sgrf_init()
64 	mmio_write_32(CRU_BASE + CRU_MODE_CON00, 0x03 << (16 + clk_pll * 2));  in set_pll_slow_mode()
75 	mmio_write_32(PMUCRU_BASE + PMUCRU_MODE_CON00, 0x000f0000);  in soc_global_soft_reset()
78 	mmio_write_32(CRU_BASE + CRU_GLB_SRST_FST, GLB_SRST_FST_CFG_VAL);  in soc_global_soft_reset()
90 	mmio_write_32(GRF_BASE + 0x0508, 0x00100010);  in rockchip_system_reset_init()
91 	mmio_write_32(CRU_BASE + 0x00dc, 0x01030103);  in rockchip_system_reset_init()