Lines Matching refs:mmio_write_32
62 mmio_write_32(PMUGRF_BASE + PMU_GRF_SOC_CON(0), WRITE_MASK_SET(BIT(7))); in pmu_pmic_sleep_mode_config()
63 mmio_write_32(PMUGRF_BASE + PMU_GRF_GPIO0A_IOMUX_L, PMIC_SLEEP_FUN); in pmu_pmic_sleep_mode_config()
69 mmio_write_32(PMU_BASE + PMU_WAKEUP_INT_CON, WRITE_MASK_SET(BIT(WAKEUP_GPIO0_INT_EN))); in pmu_wakeup_source_config()
88 mmio_write_32(PMU_BASE + PMU_PLLPD_CON, WRITE_MASK_SET(pll_id)); in pmu_pll_powerdown_config()
95 mmio_write_32(PMU_BASE + PMU_DSU_STABLE_CNT, 0x180); in pmu_stable_count_config()
96 mmio_write_32(PMU_BASE + PMU_PMIC_STABLE_CNT, 0x180); in pmu_stable_count_config()
97 mmio_write_32(PMU_BASE + PMU_OSC_STABLE_CNT, 0x180); in pmu_stable_count_config()
98 mmio_write_32(PMU_BASE + PMU_WAKEUP_RSTCLR_CNT, 0x180); in pmu_stable_count_config()
99 mmio_write_32(PMU_BASE + PMU_PLL_LOCK_CNT, 0x180); in pmu_stable_count_config()
100 mmio_write_32(PMU_BASE + PMU_DSU_PWRUP_CNT, 0x180); in pmu_stable_count_config()
101 mmio_write_32(PMU_BASE + PMU_DSU_PWRDN_CNT, 0x180); in pmu_stable_count_config()
102 mmio_write_32(PMU_BASE + PMU_GPU_VOLUP_CNT, 0x180); in pmu_stable_count_config()
103 mmio_write_32(PMU_BASE + PMU_GPU_VOLDN_CNT, 0x180); in pmu_stable_count_config()
104 mmio_write_32(PMU_BASE + PMU_WAKEUP_TIMEOUT_CNT, 0x180); in pmu_stable_count_config()
105 mmio_write_32(PMU_BASE + PMU_PWM_SWITCH_CNT, 0x180); in pmu_stable_count_config()
106 mmio_write_32(PMU_BASE + PMU_DBG_RST_CNT, 0x180); in pmu_stable_count_config()
171 mmio_write_32(PMU_BASE + PMU_PWR_GATE_CON, pwr_gate_con); in pmu_pd_powerdown_config()
172 mmio_write_32(PMU_BASE + PMU_BUS_IDLE_CON0, WRITE_MASK_SET(pmu_bus_idle_con0)); in pmu_pd_powerdown_config()
173 mmio_write_32(PMU_BASE + PMU_BUS_IDLE_CON1, WRITE_MASK_SET(pmu_bus_idle_con1)); in pmu_pd_powerdown_config()
178 mmio_write_32(PMU_BASE + PMU_NOC_AUTO_CON0, 0xffffffff); in pmu_pd_powerdown_config()
179 mmio_write_32(PMU_BASE + PMU_NOC_AUTO_CON1, 0x00070007); in pmu_pd_powerdown_config()
181 mmio_write_32(PMU_BASE + PMU_VOL_GATE_SFTCON, WRITE_MASK_SET(BIT(VD_NPU_ENA))); in pmu_pd_powerdown_config()
183 mmio_write_32(PMU_BASE + PMU_PWR_CON, WRITE_MASK_CLR(BIT(PWRDN_BYPASS))); in pmu_pd_powerdown_config()
184 mmio_write_32(PMU_BASE + PMU_PWR_CON, WRITE_MASK_CLR(BIT(BUS_BYPASS))); in pmu_pd_powerdown_config()
207 mmio_write_32(PMU_BASE + PMU_DDR_PWR_CON, WRITE_MASK_SET(pmu_ddr_pwr_con)); in pmu_ddr_suspend_config()
209 mmio_write_32(PMU_BASE + PMU_PLLPD_CON, WRITE_MASK_SET(BIT(DPLL_PD_ENA))); in pmu_ddr_suspend_config()
210 mmio_write_32(PMU_BASE + PMU_PWR_CON, WRITE_MASK_CLR(BIT(DDR_BYPASS))); in pmu_ddr_suspend_config()
214 mmio_write_32(DDRGRF_BASE + GRF_DDR_CON3, 0x00600020); in pmu_ddr_suspend_config()
246 mmio_write_32(PMU_BASE + PMU_CLUSTER_IDLE_CON, 0x000f000f); in pmu_dsu_suspend_config()
247 mmio_write_32(PMU_BASE + PMU_DSU_PWR_CON, WRITE_MASK_SET(pmu_dsu_pwr_con)); in pmu_dsu_suspend_config()
248 mmio_write_32(PMU_BASE + PMU_PWR_CON, WRITE_MASK_CLR(BIT(DSU_BYPASS))); in pmu_dsu_suspend_config()
270 mmio_write_32(PMU_BASE + PMU_PWR_CON, (0xf << (16 + CPU0_BYPASS)) | cpus_bypass); in pmu_cpu_powerdown_config()
281 mmio_write_32(PMUCRU_BASE + PMUCRU_PMUGATE_CON01, 0x38000000); in pvtm_32k_config()
282 mmio_write_32(PMUPVTM_BASE + PVTM_CON0, 0x00020002); in pvtm_32k_config()
285 mmio_write_32(PMUPVTM_BASE + PVTM_CON0, 0x001c0000); in pvtm_32k_config()
287 mmio_write_32(PMUPVTM_BASE + PVTM_CON1, PVTM_CALC_CNT); in pvtm_32k_config()
290 mmio_write_32(PMUPVTM_BASE + PVTM_CON0, 0x00010001); in pvtm_32k_config()
306 mmio_write_32(PMUGRF_BASE + PMU_GRF_DLL_CON0, pvtm_div); in pvtm_32k_config()
308 mmio_write_32(PMUCRU_BASE + PMUCRU_PMUCLKSEL_CON00, 0x00c00000); in pvtm_32k_config()
312 mmio_write_32(PMU_BASE + PMU_WAKEUP_TIMEOUT_CNT, 32000 * 10); in pvtm_32k_config()
314 mmio_write_32(PMU_BASE + PMU_CRU_PWR_CON, WRITE_MASK_SET(pmu_cru_pwr_con)); in pvtm_32k_config()
325 mmio_write_32(PMU_BASE + PMU_CRU_PWR_CON, WRITE_MASK_SET(pmu_cru_pwr_con)); in pmu_cru_suspendmode_config()
335 mmio_write_32(PMU_BASE + PMU_INT_MASK_CON, CLB_INT_DISABLE); in pmu_suspend_cru_fsm()
336 mmio_write_32(PMU_BASE + PMU_PWR_CON, CPUS_BYPASS); in pmu_suspend_cru_fsm()
340 mmio_write_32(PMU_BASE + PMU_WAKEUP_TIMEOUT_CNT, 0x5dc0 * 20000); in pmu_suspend_cru_fsm()
342 mmio_write_32(PMU_BASE + PMU_CRU_PWR_CON, WRITE_MASK_SET(BIT(ALIVE_OSC_ENA))); in pmu_suspend_cru_fsm()
351 mmio_write_32(PMU_BASE + PMU_PWR_CON, 0x00010001); in pmu_suspend_cru_fsm()
356 mmio_write_32(DDRGRF_BASE + GRF_DDR_CON3, grf_ddr_con3 | 0xffff0000); in pmu_reinit()
357 mmio_write_32(PMU_BASE + PMU_PWR_CON, 0xffff0000); in pmu_reinit()
358 mmio_write_32(PMU_BASE + PMU_INT_MASK_CON, 0xffff0000); in pmu_reinit()
359 mmio_write_32(PMU_BASE + PMU_WAKEUP_INT_CON, 0xffff0000); in pmu_reinit()
360 mmio_write_32(PMU_BASE + PMU_BUS_IDLE_CON0, 0xffff0000); in pmu_reinit()
361 mmio_write_32(PMU_BASE + PMU_DDR_PWR_CON, 0xffff0000); in pmu_reinit()
362 mmio_write_32(PMU_BASE + PMU_BUS_IDLE_CON1, 0xffff0000); in pmu_reinit()
364 mmio_write_32(PMU_BASE + PMU_PWR_GATE_CON, 0xffff0000); in pmu_reinit()
365 mmio_write_32(PMU_BASE + PMU_VOL_GATE_SFTCON, 0xffff0000); in pmu_reinit()
366 mmio_write_32(PMU_BASE + PMU_CRU_PWR_CON, 0xffff0000); in pmu_reinit()
368 mmio_write_32(PMU_BASE + PMU_PLLPD_CON, 0xffff0000); in pmu_reinit()
369 mmio_write_32(PMU_BASE + PMU_INFO_TX_CON, 0xffff0000); in pmu_reinit()
370 mmio_write_32(PMU_BASE + PMU_DSU_PWR_CON, 0xffff0000); in pmu_reinit()
371 mmio_write_32(PMU_BASE + PMU_CLUSTER_IDLE_CON, 0xffff0000); in pmu_reinit()
424 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(idx), in cpus_power_domain_off()
438 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(idx), in cpus_power_domain_on()
440 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(idx), in cpus_power_domain_on()
480 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(idx), in rockchip_soc_cores_pwr_dm_on_finish()
494 mmio_write_32(SYSSRAM_BASE + 0x04, 0xdeadbeaf); in nonboot_cpus_off()
495 mmio_write_32(SYSSRAM_BASE + 0x08, (uintptr_t)&rockchip_soc_sys_pd_pwr_dn_wfi); in nonboot_cpus_off()
522 mmio_write_32(PMU_BASE + PMU_NOC_AUTO_CON0, 0xffffffff); in plat_rockchip_pmu_init()
523 mmio_write_32(PMU_BASE + PMU_NOC_AUTO_CON1, 0x00070007); in plat_rockchip_pmu_init()
530 mmio_write_32(PMUGRF_BASE + PMU_GRF_SOC_CON(0), 0x00800080); in plat_rockchip_pmu_init()
537 mmio_write_32(SGRF_BASE + 0x008, 0x00100000); in plat_rockchip_pmu_init()
545 mmio_write_32(PMUSGRF_BASE + PMU_SGRF_SOC_CON1, 0x18000800); in plat_rockchip_pmu_init()