Lines Matching refs:mmio_write_32
94 mmio_write_32(PMU_BASE + PMU2_CPU_PWR_SFTCON(cpu), in cpu_power_domain_ctr()
150 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), in cpus_power_domain_on()
163 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), in cpus_power_domain_on()
183 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), in cpus_power_domain_off()
197 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), in cpus_power_domain_off()
233 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), in rockchip_soc_cores_pwr_dm_on_finish()
259 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), in rockchip_soc_cores_pwr_dm_resume()
289 mmio_write_32(CCI_GRF_BASE + CCIGRF_CON(4), 0xffffffff); in ddr_resume()
290 mmio_write_32(LITCORE_GRF_BASE + COREGRF_CPU_CON(1), in ddr_resume()
298 mmio_write_32(SYS_SGRF_BASE + SYSSGRF_SOC_CON(19), 0x00070000); in ddr_resume()
302 mmio_write_32(SYS_SGRF_BASE + SYSSGRF_SOC_CON(19), 0x00070000 | key_upd_msk); in ddr_resume()
312 mmio_write_32(SYS_SGRF_BASE + SYSSGRF_SOC_CON(19), 0x00700070); in ddr_resume()
326 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), in clk_gate_con_disable()
329 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), in clk_gate_con_disable()
335 mmio_write_32(PHP_CRU_BASE + PHP_CRU_CLKGATE_CON(i), 0xffff0000); in clk_gate_con_disable()
338 mmio_write_32(SECURE_CRU_BASE + SECURE_CRU_CLKGATE_CON(i), 0xffff0000); in clk_gate_con_disable()
341 mmio_write_32(SECURE_CRU_BASE + SECURE_SCRU_CLKGATE_CON(i), 0xffff0000); in clk_gate_con_disable()
344 mmio_write_32(PMU1_CRU_BASE + PMU1CRU_CLKGATE_CON(i), 0xffff0000); in clk_gate_con_disable()
347 mmio_write_32(PMU1_CRU_BASE + PMU1SCRU_CLKGATE_CON(i), 0xffff0000); in clk_gate_con_disable()
378 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), in clk_gate_con_restore()
382 mmio_write_32(PHP_CRU_BASE + PHP_CRU_CLKGATE_CON(i), in clk_gate_con_restore()
386 mmio_write_32(SECURE_CRU_BASE + SECURE_CRU_CLKGATE_CON(i), in clk_gate_con_restore()
390 mmio_write_32(SECURE_CRU_BASE + SECURE_SCRU_CLKGATE_CON(i), in clk_gate_con_restore()
394 mmio_write_32(PMU1_CRU_BASE + PMU1CRU_CLKGATE_CON(i), in clk_gate_con_restore()
398 mmio_write_32(PMU1_CRU_BASE + PMU1SCRU_CLKGATE_CON(i), in clk_gate_con_restore()
406 mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_SFTCON(bus / 16), in pmu_bus_idle_req()
434 mmio_write_32(PMU_BASE + PMU2_PWR_GATE_SFTCON(pd / 16), in pmu_power_domain_ctr()
566 mmio_write_32(PMU_BASE + PMU2_PWR_GATE_SFTCON(0), in pmu_power_domains_resume()
587 mmio_write_32(DDR_GRF_BASE + DDRGRF_CHA_CON(2), 0x0a000a00); in ddr_sleep_config()
588 mmio_write_32(DDR_GRF_BASE + DDRGRF_CHB_CON(2), 0x0a000a00); in ddr_sleep_config()
593 mmio_write_32(DDR_GRF_BASE + DDRGRF_CHA_CON(2), in ddr_sleep_config_restore()
595 mmio_write_32(DDR_GRF_BASE + DDRGRF_CHB_CON(2), in ddr_sleep_config_restore()
602 mmio_write_32(PMU0_GRF_BASE + PMU0GRF_SOC_CON(1), in sleep_pin_config()
604 mmio_write_32(PMU0_GRF_BASE + PMU0GRF_SOC_CON(0), in sleep_pin_config()
606 mmio_write_32(PMU0_IOC_BASE + PMUIO0_IOC_GPIO0A_IOMUX_SEL_L, in sleep_pin_config()
636 mmio_write_32(PMU0_IOC_BASE + PMUIO0_IOC_GPIO0A_IOMUX_SEL_L, in pmu_sleep_config()
685 mmio_write_32(PMU_BASE + PMU2_BUS_IDLEACK_BYPASS_CON, 0x00030003); in pmu_sleep_config()
686 mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_KEYUPD_CON0, 0x03ff0000); in pmu_sleep_config()
689 mmio_write_32(PMU_BASE + PMU2_BISR_GLB_CON, 0x00010000); in pmu_sleep_config()
695 mmio_write_32(SYS_SGRF_BASE + SYSSGRF_SOC_CON(19), in pmu_sleep_config()
697 mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_KEYUPD_CON1, in pmu_sleep_config()
699 mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_KEYUPD_CON1, in pmu_sleep_config()
702 mmio_write_32(PMU_BASE + PMU0_PMIC_STABLE_CNT_THRES, 24000 * 5); in pmu_sleep_config()
703 mmio_write_32(PMU_BASE + PMU0_OSC_STABLE_CNT_THRES, 24000 * 5); in pmu_sleep_config()
705 mmio_write_32(PMU_BASE + PMU1_OSC_STABLE_CNT_THRESH, 24000 * 5); in pmu_sleep_config()
706 mmio_write_32(PMU_BASE + PMU1_STABLE_CNT_THRESH, 24000 * 5); in pmu_sleep_config()
708 mmio_write_32(PMU_BASE + PMU1_SLEEP_CNT_THRESH, 24000 * 15); in pmu_sleep_config()
714 mmio_write_32(PMU_BASE + PMU0_WAKEUP_RST_CLR_CNT_THRES, 12000); in pmu_sleep_config()
716 mmio_write_32(PMU_BASE + PMU1_WAKEUP_RST_CLR_CNT_THRESH, 12000); in pmu_sleep_config()
717 mmio_write_32(PMU_BASE + PMU1_PLL_LOCK_CNT_THRESH, 12000); in pmu_sleep_config()
718 mmio_write_32(PMU_BASE + PMU1_PWM_SWITCH_CNT_THRESH, in pmu_sleep_config()
721 mmio_write_32(PMU_BASE + PMU2_SCU0_PWRUP_CNT_THRESH, 0); in pmu_sleep_config()
722 mmio_write_32(PMU_BASE + PMU2_SCU0_PWRDN_CNT_THRESH, 0); in pmu_sleep_config()
723 mmio_write_32(PMU_BASE + PMU2_SCU0_STABLE_CNT_THRESH, 0); in pmu_sleep_config()
725 mmio_write_32(PMU_BASE + PMU2_FAST_PWRUP_CNT_THRESH_0, 0); in pmu_sleep_config()
726 mmio_write_32(PMU_BASE + PMU2_FAST_PWRDN_CNT_THRESH_0, 0); in pmu_sleep_config()
727 mmio_write_32(PMU_BASE + PMU2_FAST_PWRUP_CNT_THRESH_1, 0); in pmu_sleep_config()
728 mmio_write_32(PMU_BASE + PMU2_FAST_PWRDN_CNT_THRESH_1, 0); in pmu_sleep_config()
729 mmio_write_32(PMU_BASE + PMU2_FAST_PWRUP_CNT_THRESH_2, 0); in pmu_sleep_config()
730 mmio_write_32(PMU_BASE + PMU2_FAST_PWRDN_CNT_THRESH_2, 0); in pmu_sleep_config()
731 mmio_write_32(PMU_BASE + PMU2_FAST_POWER_CON, 0xffff0007); in pmu_sleep_config()
734 mmio_write_32(PMU_BASE + PMU2_CLUSTER0_IDLE_CON, 0xffff0007); in pmu_sleep_config()
735 mmio_write_32(PMU_BASE + PMU2_CLUSTER1_IDLE_CON, 0xffff0007); in pmu_sleep_config()
739 mmio_write_32(PMU_BASE + PMU2_SCU0_PWR_CON, 0xffff020f); in pmu_sleep_config()
740 mmio_write_32(PMU_BASE + PMU2_SCU1_PWR_CON, 0xffff020f); in pmu_sleep_config()
741 mmio_write_32(PMU_BASE + PMU2_SCU0_AUTO_PWR_CON, 0x00070000); in pmu_sleep_config()
742 mmio_write_32(PMU_BASE + PMU2_SCU1_AUTO_PWR_CON, 0x00070000); in pmu_sleep_config()
744 mmio_write_32(PMU_BASE + PMU2_CCI_PWR_CON, 0xffff0009); in pmu_sleep_config()
750 mmio_write_32(PMU_BASE + PMU1_PWR_CON, WITH_16BITS_WMSK(pmu1_pwr_con)); in pmu_sleep_config()
753 mmio_write_32(PMU_BASE + PMU1_CRU_PWR_CON(0), WITH_16BITS_WMSK(pmu1cru_pwr_con)); in pmu_sleep_config()
756 mmio_write_32(PMU_BASE + PMU0_DDR_RET_CON(1), 0xffff0000); in pmu_sleep_config()
757 mmio_write_32(PMU_BASE + PMU1_DDR_PWR_CON(0), WITH_16BITS_WMSK(pmu1_ddr_pwr_con)); in pmu_sleep_config()
758 mmio_write_32(PMU_BASE + PMU1_DDR_PWR_CON(1), WITH_16BITS_WMSK(pmu1_ddr_pwr_con)); in pmu_sleep_config()
759 mmio_write_32(PMU_BASE + PMU1_DDR_AXIPWR_CON(0), 0x03ff03ff); in pmu_sleep_config()
760 mmio_write_32(PMU_BASE + PMU1_DDR_AXIPWR_CON(1), 0x03ff03ff); in pmu_sleep_config()
763 mmio_write_32(PMU_BASE + PMU1_PLLPD_CON(0), WITH_16BITS_WMSK(pmu1_pll_pd_con)); in pmu_sleep_config()
766 mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_CON(0), WITH_16BITS_WMSK(pmu2_bus_idle_con[0])); in pmu_sleep_config()
767 mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_CON(1), WITH_16BITS_WMSK(pmu2_bus_idle_con[1])); in pmu_sleep_config()
770 mmio_write_32(PMU_BASE + PMU2_PWR_GATE_CON(0), WITH_16BITS_WMSK(pmu2_pwr_gt_con[0])); in pmu_sleep_config()
771 mmio_write_32(PMU_BASE + PMU2_PWR_GATE_CON(1), WITH_16BITS_WMSK(pmu2_pwr_gt_con[1])); in pmu_sleep_config()
774 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_SFTCON(0), 0xffff0031); in pmu_sleep_config()
775 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_SFTCON(1), 0xffff0200); in pmu_sleep_config()
778 mmio_write_32(PMU_BASE + PMU1_WAKEUP_INT_CON, pmu1_wkup_int_con); in pmu_sleep_config()
781 mmio_write_32(PMU0_GRF_BASE + PMU0GRF_SOC_CON(5), 0x00400040); in pmu_sleep_config()
784 mmio_write_32(PMU0_GRF_BASE + PMU0GRF_SOC_CON(5), in pmu_sleep_config()
788 mmio_write_32(PMU_BASE + PMU2_C0_PWRACK_BYPASS_CON(0), 0x01000100); in pmu_sleep_config()
789 mmio_write_32(PMU_BASE + PMU2_C1_PWRACK_BYPASS_CON(0), 0x01000100); in pmu_sleep_config()
790 mmio_write_32(PMU_BASE + PMU2_C2_PWRACK_BYPASS_CON(0), 0x01000100); in pmu_sleep_config()
795 mmio_write_32(PMU_BASE + PMU0_INFO_TX_CON, 0xffff0000); in pmu_sleep_restore()
796 mmio_write_32(PMU_BASE + PMU2_DEBUG_INFO_SEL, 0xffff0000); in pmu_sleep_restore()
797 mmio_write_32(PMU_BASE + PMU2_CLUSTER0_IDLE_CON, 0xffff0000); in pmu_sleep_restore()
798 mmio_write_32(PMU_BASE + PMU2_SCU0_PWR_CON, 0xffff0000); in pmu_sleep_restore()
799 mmio_write_32(PMU_BASE + PMU2_CCI_PWR_CON, 0xffff0000); in pmu_sleep_restore()
800 mmio_write_32(PMU_BASE + PMU1_INT_MASK_CON, 0xffff0000); in pmu_sleep_restore()
801 mmio_write_32(PMU_BASE + PMU1_PWR_CON, 0xffff0000); in pmu_sleep_restore()
802 mmio_write_32(PMU_BASE + PMU1_CRU_PWR_CON(0), 0xffff0000); in pmu_sleep_restore()
803 mmio_write_32(PMU_BASE + PMU1_DDR_PWR_CON(0), 0xffff0000); in pmu_sleep_restore()
804 mmio_write_32(PMU_BASE + PMU1_DDR_PWR_CON(1), 0xffff0000); in pmu_sleep_restore()
805 mmio_write_32(PMU_BASE + PMU1_DDR_AXIPWR_CON(0), 0xffff0000); in pmu_sleep_restore()
806 mmio_write_32(PMU_BASE + PMU1_DDR_AXIPWR_CON(1), 0xffff0000); in pmu_sleep_restore()
807 mmio_write_32(PMU_BASE + PMU1_PLLPD_CON(0), 0xffff0000); in pmu_sleep_restore()
808 mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_CON(0), 0xffff0000); in pmu_sleep_restore()
809 mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_CON(1), 0xffff0000); in pmu_sleep_restore()
810 mmio_write_32(PMU_BASE + PMU2_PWR_GATE_CON(0), 0xffff0000); in pmu_sleep_restore()
811 mmio_write_32(PMU_BASE + PMU2_PWR_GATE_CON(1), 0xffff0000); in pmu_sleep_restore()
812 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_SFTCON(0), 0xffff0000); in pmu_sleep_restore()
813 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_SFTCON(1), 0xffff0000); in pmu_sleep_restore()
814 mmio_write_32(PMU_BASE + PMU2_BUS_IDLEACK_BYPASS_CON, 0xffff0000); in pmu_sleep_restore()
815 mmio_write_32(PMU_BASE + PMU1_WAKEUP_INT_CON, 0); in pmu_sleep_restore()
816 mmio_write_32(PMU_BASE + PMU2_FAST_POWER_CON, in pmu_sleep_restore()
818 mmio_write_32(PMU_BASE + PMU2_BISR_GLB_CON, in pmu_sleep_restore()
821 mmio_write_32(PMU_BASE + PMU2_C0_PWRACK_BYPASS_CON(0), in pmu_sleep_restore()
823 mmio_write_32(PMU_BASE + PMU2_C1_PWRACK_BYPASS_CON(0), in pmu_sleep_restore()
825 mmio_write_32(PMU_BASE + PMU2_C2_PWRACK_BYPASS_CON(0), in pmu_sleep_restore()
828 mmio_write_32(PMU0_GRF_BASE + PMU0GRF_SOC_CON(5), in pmu_sleep_restore()
838 mmio_write_32(SYS_SGRF_BASE + SYSSGRF_SOC_CON(0), in secure_watchdog_disable()
844 mmio_write_32(SYS_SGRF_BASE + SYSSGRF_SOC_CON(0), in secure_watchdog_restore()
849 mmio_write_32(WDT_S_BASE + WDT_CRR, 0x76); in secure_watchdog_restore()
878 mmio_write_32(PMU0_IOC_BASE + PMUIO0_IOC_GPIO0A_IOMUX_SEL_L, in soc_sleep_restore()
880 mmio_write_32(PMU0_IOC_BASE + PMUIO0_IOC_GPIO0A_IOMUX_SEL_H, in soc_sleep_restore()
882 mmio_write_32(PMU0_IOC_BASE + PMUIO0_IOC_GPIO0B_IOMUX_SEL_L, in soc_sleep_restore()
885 mmio_write_32(PMU0_GRF_BASE + PMU0GRF_SOC_CON(1), in soc_sleep_restore()
887 mmio_write_32(PMU0_GRF_BASE + PMU0GRF_SOC_CON(0), in soc_sleep_restore()
897 mmio_write_32(CRU_BASE + 0x280, 0x03ff0000); in pm_pll_suspend()
898 mmio_write_32(SECURE_CRU_BASE + 0x4280, 0x00030000); in pm_pll_suspend()
901 mmio_write_32(PMU1_CRU_BASE + PMU1CRU_CLKSEL_CON(4), in pm_pll_suspend()
907 mmio_write_32(CRU_BASE + 0x280, WITH_16BITS_WMSK(ddr_data.cru_mode_con)); in pm_pll_restore()
908 mmio_write_32(SECURE_CRU_BASE + 0x4280, in pm_pll_restore()
957 mmio_write_32(PMU1_GRF_BASE + PMU1GRF_OS_REG(0), BOOT_BROM_DOWNLOAD); in rockchip_soc_soft_reset_check_rstout()
960 mmio_write_32(PMU1SGRF_BASE + PMU1SGRF_SOC_CON(0), 0x00070000); in rockchip_soc_soft_reset_check_rstout()
963 mmio_write_32(PMU0SGRF_BASE + PMU0SGRF_SOC_CON(1), 0xffff0000); in rockchip_soc_soft_reset_check_rstout()
964 mmio_write_32(PMU1SGRF_BASE + PMU1SGRF_SOC_CON(16), 0xffff0000); in rockchip_soc_soft_reset_check_rstout()
965 mmio_write_32(PMU1SGRF_BASE + PMU1SGRF_SOC_CON(17), 0xffff0000); in rockchip_soc_soft_reset_check_rstout()
974 mmio_write_32(CRU_BASE + CRU_MODE_CON, 0x003f0000); in rockchip_soc_soft_reset()
980 mmio_write_32(CRU_BASE + CRU_GLB_SRST_FST, GLB_SRST_FST_CFG_VAL); in rockchip_soc_soft_reset()
996 mmio_write_32(GPIO0_BASE + GPIO_SWPORT_DDR_L, in rockchip_soc_system_off()
1000 mmio_write_32(GPIO0_BASE + GPIO_SWPORT_DR_L, in rockchip_soc_system_off()
1017 mmio_write_32(PMU_BASE + PMU2_BISR_PDGEN_CON(1), in rockchip_pmu_pd_repair_init()
1041 mmio_write_32(PMU_BASE + PMU2_NOC_AUTO_CON(0), 0xffffffff); in plat_rockchip_pmu_init()
1042 mmio_write_32(PMU_BASE + PMU2_NOC_AUTO_CON(1), 0xffffffff); in plat_rockchip_pmu_init()
1045 mmio_write_32(PMU0SGRF_BASE + PMU0SGRF_SOC_CON(2), BITS_WITH_WMASK(1, 0x3, 0)); in plat_rockchip_pmu_init()
1048 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_SFTCON(0), in plat_rockchip_pmu_init()