24 	mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(0), (0x7 << 24) | (0x7 << 16));  in ddr_pll_bypass_100mts()
25 	mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_SET(0), (0x2 << 24));  in ddr_pll_bypass_100mts()
28 	mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1), (0x7 << 24) | (0x7 << 16));  in ddr_pll_bypass_100mts()
29 	mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1), (0x2 << 24) | (0x1 << 16));  in ddr_pll_bypass_100mts()
32 	mmio_write_32(DRAM_SEL_CFG + 0x4, BIT(24));  in ddr_pll_bypass_100mts()
38 	mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(0), (0x7 << 24) | (0x7 << 16));  in ddr_pll_bypass_400mts()
39 	mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_SET(0), (0x1 << 24) | (0x1 << 16));  in ddr_pll_bypass_400mts()
42 	mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1), (0x7 << 24) | (0x7 << 16));  in ddr_pll_bypass_400mts()
43 	mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1), (0x3 << 24) | (0x1 << 16));  in ddr_pll_bypass_400mts()
46 	mmio_write_32(DRAM_SEL_CFG + 0x4, BIT(24));  in ddr_pll_bypass_400mts()
51 	mmio_write_32(DRAM_SEL_CFG + 0x8, BIT(24));  in ddr_pll_unbypass()
52 	mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1), (0x7 << 24) | (0x7 << 16));  in ddr_pll_unbypass()
54 	mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1), (0x4 << 24) | (0x4 << 16));  in ddr_pll_unbypass()
65 		mmio_write_32(HW_DRAM_PLL_CFG2, PLL_FREQ_800M);  in dram_pll_init()
68 		mmio_write_32(HW_DRAM_PLL_CFG2, PLL_FREQ_400M);  in dram_pll_init()
71 		mmio_write_32(HW_DRAM_PLL_CFG2, PLL_FREQ_167M);  in dram_pll_init()
92 		mmio_write_32(DRAM_PLL_CTRL + 0x4, (250 << 12) | (3 << 4) | 1);  in dram_pll_init()
97 		mmio_write_32(DRAM_PLL_CTRL + 0x4, (311 << 12) | (4 << 4) | 1);  in dram_pll_init()
100 		mmio_write_32(DRAM_PLL_CTRL + 0x4, (300 << 12) | (8 << 4) | 0);  in dram_pll_init()
103 		mmio_write_32(DRAM_PLL_CTRL + 0x4, (300 << 12) | (9 << 4) | 0);  in dram_pll_init()
106 		mmio_write_32(DRAM_PLL_CTRL + 0x4, (300 << 12) | (3 << 4) | 2);  in dram_pll_init()
109 		mmio_write_32(DRAM_PLL_CTRL + 0x4, (400 << 12) | (3 << 4) | 3);  in dram_pll_init()
112 		mmio_write_32(DRAM_PLL_CTRL + 0x4, (266 << 12) | (3 << 4) | 3);  in dram_pll_init()
115 		mmio_write_32(DRAM_PLL_CTRL + 0x4, (334 << 12) | (3 << 4) | 4);  in dram_pll_init()