Lines Matching refs:mmio_write_32
36 mmio_write_32(DDRC_DRAMTMG2(0) + offset, dram_info.rank_setting[i][0]); in rank_setting_update()
38 mmio_write_32(DDRC_DRAMTMG9(0) + offset, dram_info.rank_setting[i][1]); in rank_setting_update()
42 mmio_write_32(DDRC_RANKCTL(0) + offset, in rank_setting_update()
47 mmio_write_32(DDRC_RANKCTL(0), dram_info.rank_setting[0][2]); in rank_setting_update()
59 mmio_write_32(DDRC_PCTRL_0(0), 0x0); in dram_enter_retention()
66 mmio_write_32(DDRC_PWRCTL(0), 0xaa); in dram_enter_retention()
79 mmio_write_32(DDRC_DFIMISC(0), 0x0); in dram_enter_retention()
80 mmio_write_32(DDRC_SWCTL(0), 0x0); in dram_enter_retention()
81 mmio_write_32(DDRC_DFIMISC(0), 0x1f00); in dram_enter_retention()
82 mmio_write_32(DDRC_DFIMISC(0), 0x1f20); in dram_enter_retention()
88 mmio_write_32(DDRC_DFIMISC(0), 0x1f00); in dram_enter_retention()
94 mmio_write_32(DDRC_SWCTL(0), 0x1); in dram_enter_retention()
110 mmio_write_32(SRC_DDR1_RCR, 0x8F000008); in dram_enter_retention()
112 mmio_write_32(CCM_CCGR(5), 0); in dram_enter_retention()
113 mmio_write_32(CCM_SRC_CTRL(15), 2); in dram_enter_retention()
127 mmio_write_32(SRC_DDR2_RCR, 0x8F000003); in dram_exit_retention()
128 mmio_write_32(SRC_DDR1_RCR, 0x8F00000F); in dram_exit_retention()
129 mmio_write_32(SRC_DDR2_RCR, 0x8F000000); in dram_exit_retention()
131 mmio_write_32(SRC_DDR1_RCR, 0x8F00001F); in dram_exit_retention()
132 mmio_write_32(SRC_DDR1_RCR, 0x8F00000F); in dram_exit_retention()
134 mmio_write_32(CCM_CCGR(5), 2); in dram_exit_retention()
135 mmio_write_32(CCM_SRC_CTRL(15), 2); in dram_exit_retention()
138 mmio_write_32(CCM_TARGET_ROOT(65) + 0x8, (0x7 << 24) | (0x7 << 16)); in dram_exit_retention()
139 mmio_write_32(CCM_TARGET_ROOT(65) + 0x4, (0x4 << 24) | (0x3 << 16)); in dram_exit_retention()
143 mmio_write_32(SRC_DDR1_RCR, 0x8F000006); in dram_exit_retention()
159 mmio_write_32(DDRC_PWRCTL(0), 0xaa); in dram_exit_retention()
160 mmio_write_32(DDRC_DBG1(0), 0x0); in dram_exit_retention()
161 mmio_write_32(SRC_DDR1_RCR, 0x8F000004); in dram_exit_retention()
162 mmio_write_32(SRC_DDR1_RCR, 0x8F000000); in dram_exit_retention()
165 mmio_write_32(DDRC_SWCTL(0), 0x0); in dram_exit_retention()
169 mmio_write_32(DDRC_DDR_SS_GPR0, 0x01); /*LPDDR4 mode */ in dram_exit_retention()
173 mmio_write_32(DDRC_DFIMISC(0), 0x0); in dram_exit_retention()
189 mmio_write_32(DDRC_SWCTL(0), 0x0); in dram_exit_retention()
190 mmio_write_32(DDRC_DFIMISC(0), 0x20); in dram_exit_retention()
197 mmio_write_32(DDRC_DFIMISC(0), 0x0); in dram_exit_retention()
199 mmio_write_32(DDRC_DFIMISC(0), 0x1); in dram_exit_retention()
202 mmio_write_32(DDRC_SWCTL(0), 0x1); in dram_exit_retention()
208 mmio_write_32(DDRC_PWRCTL(0), 0x88); in dram_exit_retention()
214 mmio_write_32(DDRC_PCTRL_0(0), 0x1); in dram_exit_retention()
216 mmio_write_32(DDRC_RFSHCTL3(0), 0x0); in dram_exit_retention()