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Searched refs:arg1 (Results 1 – 25 of 192) sorted by relevance

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/rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv5_4/
H A Dmt_cpu_pm_smc.c33 u_register_t arg1, in cpupm_dispatcher() argument
42 res = mtk_cpc_handler(act, arg1, arg2); in cpupm_dispatcher()
53 u_register_t arg1, in cpupm_lp_dispatcher() argument
64 res = mtk_cpc_handler(act, arg1, arg2); in cpupm_lp_dispatcher()
89 .val = (unsigned int)arg1, in cpupm_lp_dispatcher()
99 ret = mt_lp_irqremain_get((unsigned int)arg1, in cpupm_lp_dispatcher()
114 (unsigned int)arg1); in cpupm_lp_dispatcher()
121 mtk_cpu_pm_counter_enable((bool)arg1); in cpupm_lp_dispatcher()
127 if (arg1 == 0) in cpupm_lp_dispatcher()
129 else if (arg1 == 1) in cpupm_lp_dispatcher()
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/dfd/
H A Ddfd.c13 static u_register_t dfd_smc_dispatcher(u_register_t arg0, u_register_t arg1, in dfd_smc_dispatcher() argument
22 dfd_setup(arg1, arg2, arg3); in dfd_smc_dispatcher()
26 if (arg1 <= 0x200) { in dfd_smc_dispatcher()
27 ret = mmio_read_32(MISC1_CFG_BASE + arg1); in dfd_smc_dispatcher()
32 if (arg1 <= 0x200) { in dfd_smc_dispatcher()
33 sync_writel(MISC1_CFG_BASE + arg1, arg2); in dfd_smc_dispatcher()
/rk3399_ARM-atf/plat/xilinx/common/include/
H A Dpm_api_sys.h62 #define PM_PACK_PAYLOAD2(pl, mid, flag, arg0, arg1) { \ argument
63 pl[1] = (uint32_t)(arg1); \
67 #define PM_PACK_PAYLOAD3(pl, mid, flag, arg0, arg1, arg2) { \ argument
69 PM_PACK_PAYLOAD2(pl, (mid), (flag), (arg0), (arg1)); \
72 #define PM_PACK_PAYLOAD4(pl, mid, flag, arg0, arg1, arg2, arg3) { \ argument
74 PM_PACK_PAYLOAD3(pl, (mid), (flag), (arg0), (arg1), (arg2)); \
77 #define PM_PACK_PAYLOAD5(pl, mid, flag, arg0, arg1, arg2, arg3, arg4) { \ argument
79 PM_PACK_PAYLOAD4(pl, (mid), (flag), (arg0), (arg1), (arg2), (arg3)); \
82 #define PM_PACK_PAYLOAD6(pl, mid, flag, arg0, arg1, arg2, arg3, arg4, arg5) { \ argument
84 PM_PACK_PAYLOAD5(pl, (mid), (flag), (arg0), (arg1), (arg2), (arg3), (arg4)); \
[all …]
/rk3399_ARM-atf/plat/arm/board/juno/
H A Djuno_bl31_setup.c17 u_register_t arg1, u_register_t arg2, u_register_t arg3) in bl31_early_platform_setup2() argument
25 INFO("BL31 FCONF: FW_CONFIG address = %lx\n", (uintptr_t)arg1); in bl31_early_platform_setup2()
28 fconf_populate("FW_CONFIG", arg1); in bl31_early_platform_setup2()
32 arg1 = soc_fw_config_info->config_addr; in bl31_early_platform_setup2()
36 arm_bl31_early_platform_setup(arg0, arg1, arg2, arg3); in bl31_early_platform_setup2()
/rk3399_ARM-atf/bl32/tsp/
H A Dtsp_private.h52 uint64_t arg1,
60 uint64_t arg1,
68 uint64_t arg1,
77 uint64_t arg1,
107 uint64_t arg1,
116 uint64_t arg1,
125 uint64_t arg1,
134 uint64_t arg1,
H A Dtsp_common.c35 uint64_t arg1, in set_smc_args() argument
53 write_sp_arg(pcpu_smc_args, SMC_ARG1, arg1); in set_smc_args()
67 void tsp_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2, in tsp_setup() argument
74 tsp_early_platform_setup(arg0, arg1, arg2, arg3); in tsp_setup()
85 uint64_t arg1, in tsp_system_off_main() argument
113 uint64_t arg1, in tsp_system_reset_main() argument
143 uint64_t arg1, in tsp_abort_smc_handler() argument
H A Dtsp_ffa_main.c84 uint64_t arg1, in ffa_test_relay() argument
281 uint64_t arg1, in tsp_cpu_off_main() argument
319 uint64_t arg1, in tsp_cpu_suspend_main() argument
356 uint64_t arg1, in tsp_cpu_resume_main() argument
389 uint64_t arg1, in handle_framework_message() argument
398 if (ffa_endpoint_source(arg1) != spmc_id) { in handle_framework_message()
406 return tsp_cpu_off_main(arg0, arg1, arg2, arg3, in handle_framework_message()
409 return tsp_cpu_suspend_main(arg0, arg1, arg2, arg3, in handle_framework_message()
415 return tsp_cpu_resume_main(arg0, arg1, arg2, arg3, in handle_framework_message()
429 uint64_t arg1, in handle_partition_message() argument
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/dfd/
H A Dplat_dfd.c112 uint64_t dfd_smc_dispatcher(uint64_t arg0, uint64_t arg1, in dfd_smc_dispatcher() argument
119 dfd_setup(arg1, arg2, arg3); in dfd_smc_dispatcher()
123 if (arg1 <= 0x200) { in dfd_smc_dispatcher()
124 ret = mmio_read_32(MISC1_CFG_BASE + arg1); in dfd_smc_dispatcher()
129 if (arg1 <= 0x200) { in dfd_smc_dispatcher()
130 sync_writel(MISC1_CFG_BASE + arg1, arg2); in dfd_smc_dispatcher()
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/dfd/
H A Dplat_dfd.c70 uint64_t dfd_smc_dispatcher(uint64_t arg0, uint64_t arg1, in dfd_smc_dispatcher() argument
78 dfd_setup(arg1, arg2, arg3); in dfd_smc_dispatcher()
82 if (arg1 <= 0x200) { in dfd_smc_dispatcher()
83 ret = mmio_read_32(MISC1_CFG_BASE + arg1); in dfd_smc_dispatcher()
88 if (arg1 <= 0x200) { in dfd_smc_dispatcher()
89 sync_writel(MISC1_CFG_BASE + arg1, arg2); in dfd_smc_dispatcher()
/rk3399_ARM-atf/drivers/arm/css/scmi/
H A Dscmi_private.h97 #define SCMI_PAYLOAD_ARG1(payld_arr, arg1) \ argument
98 mmio_write_32((uintptr_t)&payld_arr[0], arg1)
100 #define SCMI_PAYLOAD_ARG2(payld_arr, arg1, arg2) do { \ argument
101 SCMI_PAYLOAD_ARG1(payld_arr, arg1); \
105 #define SCMI_PAYLOAD_ARG3(payld_arr, arg1, arg2, arg3) do { \ argument
106 SCMI_PAYLOAD_ARG2(payld_arr, arg1, arg2); \
110 #define SCMI_PAYLOAD_ARG4(payld_arr, arg1, arg2, arg3, arg4) do { \ argument
111 SCMI_PAYLOAD_ARG3(payld_arr, arg1, arg2, arg3); \
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/dfd/
H A Dplat_dfd.c128 uint64_t dfd_smc_dispatcher(uint64_t arg0, uint64_t arg1, in dfd_smc_dispatcher() argument
136 dfd_setup(arg1, arg2, arg3); in dfd_smc_dispatcher()
140 if (arg1 <= 0x200) { in dfd_smc_dispatcher()
141 ret = mmio_read_32(MISC1_CFG_BASE + arg1); in dfd_smc_dispatcher()
146 if (arg1 <= 0x200) { in dfd_smc_dispatcher()
147 sync_writel(MISC1_CFG_BASE + arg1, arg2); in dfd_smc_dispatcher()
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t186/drivers/mce/
H A Dmce.c158 int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, in mce_command_handler() argument
177 ret = ops->enter_cstate(cpu_ari_base, arg0, arg1); in mce_command_handler()
191 (uint32_t)arg1, (uint32_t)arg2, (uint8_t)arg3, in mce_command_handler()
201 ret = ops->update_crossover_time(cpu_ari_base, arg0, arg1); in mce_command_handler()
215 ret = ops->write_cstate_stats(cpu_ari_base, arg0, arg1); in mce_command_handler()
220 ret = ops->is_ccx_allowed(cpu_ari_base, arg0, arg1); in mce_command_handler()
228 ret = ops->is_sc7_allowed(cpu_ari_base, arg0, arg1); in mce_command_handler()
242 ret = ops->cc3_ctrl(cpu_ari_base, arg0, arg1, arg2); in mce_command_handler()
296 ret64 = ops->read_write_mca(cpu_ari_base, arg0, &arg1); in mce_command_handler()
300 write_ctx_reg(gp_regs, CTX_GPREG_X2, (arg1)); in mce_command_handler()
[all …]
/rk3399_ARM-atf/plat/xilinx/zynqmp/pm_service/
H A Dpm_api_ioctl.c678 uint32_t arg1, in pm_api_ioctl() argument
691 ret = pm_ioctl_set_rpu_oper_mode(arg1); in pm_api_ioctl()
694 ret = pm_ioctl_config_boot_addr(nid, arg1); in pm_api_ioctl()
697 ret = pm_ioctl_config_tcm_comb(arg1); in pm_api_ioctl()
700 ret = pm_ioctl_set_tapdelay_bypass(arg1, arg2, flag); in pm_api_ioctl()
703 ret = pm_ioctl_sd_dll_reset(nid, arg1, flag); in pm_api_ioctl()
706 ret = pm_ioctl_sd_set_tapdelay(nid, arg1, arg2, flag); in pm_api_ioctl()
709 ret = pm_ioctl_set_pll_frac_mode(arg1, arg2); in pm_api_ioctl()
712 ret = pm_ioctl_get_pll_frac_mode(arg1, value); in pm_api_ioctl()
715 ret = pm_ioctl_set_pll_frac_data(arg1, arg2, flag); in pm_api_ioctl()
[all …]
H A Dzynqmp_pm_api_sys.h45 #define PM_PACK_PAYLOAD2(pl, flag, arg0, arg1) { \ argument
46 pl[1] = (uint32_t)(arg1); \
50 #define PM_PACK_PAYLOAD3(pl, flag, arg0, arg1, arg2) { \ argument
52 PM_PACK_PAYLOAD2(pl, (flag), (arg0), (arg1)); \
55 #define PM_PACK_PAYLOAD4(pl, flag, arg0, arg1, arg2, arg3) { \ argument
57 PM_PACK_PAYLOAD3(pl, (flag), (arg0), (arg1), (arg2)); \
60 #define PM_PACK_PAYLOAD5(pl, flag, arg0, arg1, arg2, arg3, arg4) { \ argument
62 PM_PACK_PAYLOAD4(pl, (flag), (arg0), (arg1), (arg2), (arg3)); \
65 #define PM_PACK_PAYLOAD6(pl, flag, arg0, arg1, arg2, arg3, arg4, arg5) { \ argument
67 PM_PACK_PAYLOAD5(pl, (flag), (arg0), (arg1), (arg2), (arg3), (arg4)); \
[all …]
/rk3399_ARM-atf/plat/arm/board/fvp/sp_min/
H A Dfvp_sp_min_setup.c19 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, in plat_arm_sp_min_early_platform_setup() argument
45 INFO("SP_MIN FCONF: FW_CONFIG address = %lx\n", (uintptr_t)arg1); in plat_arm_sp_min_early_platform_setup()
47 fconf_populate("FW_CONFIG", arg1); in plat_arm_sp_min_early_platform_setup()
51 arg1 = tos_fw_config_info->config_addr; in plat_arm_sp_min_early_platform_setup()
56 arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3); in plat_arm_sp_min_early_platform_setup()
/rk3399_ARM-atf/plat/arm/board/fvp/
H A Dfvp_bl31_setup.c26 u_register_t arg1, u_register_t arg2, u_register_t arg3) in bl31_early_platform_setup2() argument
34 INFO("BL31 FCONF: FW_CONFIG address = %lx\n", (uintptr_t)arg1); in bl31_early_platform_setup2()
36 fconf_populate("FW_CONFIG", arg1); in bl31_early_platform_setup2()
40 arg1 = soc_fw_config_info->config_addr; in bl31_early_platform_setup2()
55 arm_bl31_early_platform_setup(arg0, arg1, arg2, arg3); in bl31_early_platform_setup2()
/rk3399_ARM-atf/plat/st/stm32mp2/
H A Dbl31_plat_setup.c21 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl31_early_platform_setup2() argument
42 mmap_add_region(arg1, arg1, STM32MP_SOC_FW_CONFIG_MAX_SIZE, MT_RO_DATA | MT_SECURE); in bl31_early_platform_setup2()
53 ret = dt_open_and_check(arg1); in bl31_early_platform_setup2()
101 bl33_image_ep_info.args.arg1 = 0U; in bl31_early_platform_setup2()
/rk3399_ARM-atf/plat/arm/board/fvp_ve/sp_min/
H A Dfvp_ve_sp_min_setup.c11 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, in plat_arm_sp_min_early_platform_setup() argument
14 arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3); in plat_arm_sp_min_early_platform_setup()
/rk3399_ARM-atf/plat/arm/board/corstone700/sp_min/
H A Dcorstone700_sp_min_setup.c9 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, in plat_arm_sp_min_early_platform_setup() argument
12 arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3); in plat_arm_sp_min_early_platform_setup()
/rk3399_ARM-atf/plat/arm/board/fvp/tsp/
H A Dfvp_tsp_setup.c11 void tsp_early_platform_setup(u_register_t arg0, u_register_t arg1, in tsp_early_platform_setup() argument
14 arm_tsp_early_platform_setup(arg0, arg1, arg2, arg3); in tsp_early_platform_setup()
/rk3399_ARM-atf/plat/amd/versal2/
H A Dplat_psci.c167 uint32_t arg1, uint32_t arg2) in no_pm_ioctl() argument
170 VERBOSE("%s: ioctl_id: %x, arg1: %x\n", __func__, ioctl_id, arg1); in no_pm_ioctl()
174 if ((arg1 == 0) || (arg1 == 1)) { in no_pm_ioctl()
176 (arg1 ? LINEAR_MODE : 0)); in no_pm_ioctl()
185 if (arg1 == 1U) { in no_pm_ioctl()
187 } else if (arg1 == 0U) { in no_pm_ioctl()
/rk3399_ARM-atf/services/arm_arch_svc/
H A Darm_arch_svc_setup.c23 static int32_t smccc_arch_features(u_register_t arg1) in smccc_arch_features() argument
25 switch (arg1) { in smccc_arch_features()
30 return plat_is_smccc_feature_available(arg1); in smccc_arch_features()
133 static uintptr_t smccc_arch_id(u_register_t arg1, void *handle, uint32_t is_smc64) in smccc_arch_id() argument
135 if (arg1 == SMCCC_GET_SOC_REVISION) { in smccc_arch_id()
138 if (arg1 == SMCCC_GET_SOC_VERSION) { in smccc_arch_id()
143 if ((arg1 == SMCCC_GET_SOC_NAME) && is_smc64) { in smccc_arch_id()
/rk3399_ARM-atf/plat/arm/board/a5ds/sp_min/
H A Da5ds_sp_min_setup.c11 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, in plat_arm_sp_min_early_platform_setup() argument
14 arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3); in plat_arm_sp_min_early_platform_setup()
/rk3399_ARM-atf/plat/arm/common/sp_min/
H A Darm_sp_min_setup.c86 void arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, in arm_sp_min_early_platform_setup() argument
125 bl33_image_ep_info.args.arg1 = ~0U; in arm_sp_min_early_platform_setup()
164 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, in plat_arm_sp_min_early_platform_setup() argument
167 arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3); in plat_arm_sp_min_early_platform_setup()
188 void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, in sp_min_early_platform_setup2() argument
191 plat_arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3); in sp_min_early_platform_setup2()
/rk3399_ARM-atf/plat/arm/board/a5ds/
H A Da5ds_bl2_setup.c9 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl2_early_platform_setup2() argument
12 arm_bl2_early_platform_setup(arg0, arg1, arg2, arg3); in bl2_early_platform_setup2()

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