1*e46e9df0SRex-BC Chen /*
2*e46e9df0SRex-BC Chen * Copyright (c) 2022, MediaTek Inc. All rights reserved.
3*e46e9df0SRex-BC Chen *
4*e46e9df0SRex-BC Chen * SPDX-License-Identifier: BSD-3-Clause
5*e46e9df0SRex-BC Chen */
6*e46e9df0SRex-BC Chen
7*e46e9df0SRex-BC Chen #include <arch_helpers.h>
8*e46e9df0SRex-BC Chen #include <common/debug.h>
9*e46e9df0SRex-BC Chen #include <lib/mmio.h>
10*e46e9df0SRex-BC Chen #include <mtk_sip_svc.h>
11*e46e9df0SRex-BC Chen #include <plat_dfd.h>
12*e46e9df0SRex-BC Chen
13*e46e9df0SRex-BC Chen static bool dfd_enabled;
14*e46e9df0SRex-BC Chen static uint64_t dfd_base_addr;
15*e46e9df0SRex-BC Chen static uint64_t dfd_chain_length;
16*e46e9df0SRex-BC Chen static uint64_t dfd_cache_dump;
17*e46e9df0SRex-BC Chen
dfd_setup(uint64_t base_addr,uint64_t chain_length,uint64_t cache_dump)18*e46e9df0SRex-BC Chen static void dfd_setup(uint64_t base_addr, uint64_t chain_length,
19*e46e9df0SRex-BC Chen uint64_t cache_dump)
20*e46e9df0SRex-BC Chen {
21*e46e9df0SRex-BC Chen mmio_write_32(MCUSYS_DFD_MAP, base_addr >> 24);
22*e46e9df0SRex-BC Chen mmio_write_32(WDT_DEBUG_CTL, WDT_DEBUG_CTL_VAL_0);
23*e46e9df0SRex-BC Chen
24*e46e9df0SRex-BC Chen sync_writel(DFD_INTERNAL_CTL, (BIT(0) | BIT(2)));
25*e46e9df0SRex-BC Chen
26*e46e9df0SRex-BC Chen mmio_setbits_32(DFD_INTERNAL_CTL, BIT(13));
27*e46e9df0SRex-BC Chen mmio_setbits_32(DFD_INTERNAL_CTL, BIT(3));
28*e46e9df0SRex-BC Chen mmio_setbits_32(DFD_INTERNAL_CTL, (BIT(19) | BIT(20)));
29*e46e9df0SRex-BC Chen mmio_write_32(DFD_INTERNAL_PWR_ON, (BIT(0) | BIT(1) | BIT(3)));
30*e46e9df0SRex-BC Chen mmio_write_32(DFD_CHAIN_LENGTH0, chain_length);
31*e46e9df0SRex-BC Chen mmio_write_32(DFD_INTERNAL_SHIFT_CLK_RATIO, 0);
32*e46e9df0SRex-BC Chen mmio_write_32(DFD_INTERNAL_TEST_SO_0, DFD_INTERNAL_TEST_SO_0_VAL);
33*e46e9df0SRex-BC Chen mmio_write_32(DFD_INTERNAL_NUM_OF_TEST_SO_GROUP, 1);
34*e46e9df0SRex-BC Chen
35*e46e9df0SRex-BC Chen mmio_write_32(DFD_TEST_SI_0, DFD_TEST_SI_0_VAL);
36*e46e9df0SRex-BC Chen mmio_write_32(DFD_TEST_SI_1, DFD_TEST_SI_1_VAL);
37*e46e9df0SRex-BC Chen
38*e46e9df0SRex-BC Chen sync_writel(DFD_V30_CTL, 1);
39*e46e9df0SRex-BC Chen
40*e46e9df0SRex-BC Chen mmio_write_32(DFD_V30_BASE_ADDR, (base_addr & 0xFFF00000));
41*e46e9df0SRex-BC Chen
42*e46e9df0SRex-BC Chen /* setup global variables for suspend and resume */
43*e46e9df0SRex-BC Chen dfd_enabled = true;
44*e46e9df0SRex-BC Chen dfd_base_addr = base_addr;
45*e46e9df0SRex-BC Chen dfd_chain_length = chain_length;
46*e46e9df0SRex-BC Chen dfd_cache_dump = cache_dump;
47*e46e9df0SRex-BC Chen
48*e46e9df0SRex-BC Chen if ((cache_dump & DFD_CACHE_DUMP_ENABLE) != 0UL) {
49*e46e9df0SRex-BC Chen mmio_write_32(WDT_DEBUG_CTL, WDT_DEBUG_CTL_VAL_1);
50*e46e9df0SRex-BC Chen sync_writel(DFD_V35_ENALBE, 1);
51*e46e9df0SRex-BC Chen sync_writel(DFD_V35_TAP_NUMBER, DFD_V35_TAP_NUMBER_VAL);
52*e46e9df0SRex-BC Chen sync_writel(DFD_V35_TAP_EN, DFD_V35_TAP_EN_VAL);
53*e46e9df0SRex-BC Chen sync_writel(DFD_V35_SEQ0_0, DFD_V35_SEQ0_0_VAL);
54*e46e9df0SRex-BC Chen
55*e46e9df0SRex-BC Chen if (cache_dump & DFD_PARITY_ERR_TRIGGER) {
56*e46e9df0SRex-BC Chen sync_writel(DFD_HW_TRIGGER_MASK, DFD_HW_TRIGGER_MASK_VAL);
57*e46e9df0SRex-BC Chen mmio_setbits_32(DFD_INTERNAL_CTL, BIT(4));
58*e46e9df0SRex-BC Chen }
59*e46e9df0SRex-BC Chen }
60*e46e9df0SRex-BC Chen dsbsy();
61*e46e9df0SRex-BC Chen }
62*e46e9df0SRex-BC Chen
dfd_resume(void)63*e46e9df0SRex-BC Chen void dfd_resume(void)
64*e46e9df0SRex-BC Chen {
65*e46e9df0SRex-BC Chen if (dfd_enabled == true) {
66*e46e9df0SRex-BC Chen dfd_setup(dfd_base_addr, dfd_chain_length, dfd_cache_dump);
67*e46e9df0SRex-BC Chen }
68*e46e9df0SRex-BC Chen }
69*e46e9df0SRex-BC Chen
dfd_smc_dispatcher(uint64_t arg0,uint64_t arg1,uint64_t arg2,uint64_t arg3)70*e46e9df0SRex-BC Chen uint64_t dfd_smc_dispatcher(uint64_t arg0, uint64_t arg1,
71*e46e9df0SRex-BC Chen uint64_t arg2, uint64_t arg3)
72*e46e9df0SRex-BC Chen {
73*e46e9df0SRex-BC Chen uint64_t ret = 0L;
74*e46e9df0SRex-BC Chen
75*e46e9df0SRex-BC Chen switch (arg0) {
76*e46e9df0SRex-BC Chen case PLAT_MTK_DFD_SETUP_MAGIC:
77*e46e9df0SRex-BC Chen INFO("[%s] DFD setup call from kernel\n", __func__);
78*e46e9df0SRex-BC Chen dfd_setup(arg1, arg2, arg3);
79*e46e9df0SRex-BC Chen break;
80*e46e9df0SRex-BC Chen case PLAT_MTK_DFD_READ_MAGIC:
81*e46e9df0SRex-BC Chen /* only allow to access DFD register base + 0x200 */
82*e46e9df0SRex-BC Chen if (arg1 <= 0x200) {
83*e46e9df0SRex-BC Chen ret = mmio_read_32(MISC1_CFG_BASE + arg1);
84*e46e9df0SRex-BC Chen }
85*e46e9df0SRex-BC Chen break;
86*e46e9df0SRex-BC Chen case PLAT_MTK_DFD_WRITE_MAGIC:
87*e46e9df0SRex-BC Chen /* only allow to access DFD register base + 0x200 */
88*e46e9df0SRex-BC Chen if (arg1 <= 0x200) {
89*e46e9df0SRex-BC Chen sync_writel(MISC1_CFG_BASE + arg1, arg2);
90*e46e9df0SRex-BC Chen }
91*e46e9df0SRex-BC Chen break;
92*e46e9df0SRex-BC Chen default:
93*e46e9df0SRex-BC Chen ret = MTK_SIP_E_INVALID_PARAM;
94*e46e9df0SRex-BC Chen break;
95*e46e9df0SRex-BC Chen }
96*e46e9df0SRex-BC Chen
97*e46e9df0SRex-BC Chen return ret;
98*e46e9df0SRex-BC Chen }
99