Home
last modified time | relevance | path

Searched refs:SPM_BASE (Results 1 – 25 of 37) sorted by relevance

12

/rk3399_ARM-atf/plat/mediatek/mt8188/include/
H A Dspm_reg.h13 #define MD32PCM_CFG_BASE (SPM_BASE + 0xA00)
14 #define POWERON_CONFIG_EN (SPM_BASE + 0x000)
15 #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004)
16 #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008)
17 #define SPM_CLK_CON (SPM_BASE + 0x00C)
18 #define SPM_CLK_SETTLE (SPM_BASE + 0x010)
19 #define SPM_AP_STANDBY_CON (SPM_BASE + 0x014)
20 #define PCM_CON0 (SPM_BASE + 0x018)
21 #define PCM_CON1 (SPM_BASE + 0x01C)
22 #define SPM_POWER_ON_VAL2 (SPM_BASE + 0x020)
[all …]
H A Dplatform_def.h61 #define SPM_BASE (IO_PHYS + 0x00006000) macro
154 #define SPM_BASE (IO_PHYS + 0x00006000) macro
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spm/
H A Dmt_spm_reg.h23 #define POWERON_CONFIG_EN (SPM_BASE + 0x000)
24 #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004)
25 #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008)
26 #define SPM_CLK_CON (SPM_BASE + 0x00C)
27 #define SPM_CLK_SETTLE (SPM_BASE + 0x010)
28 #define SPM_AP_STANDBY_CON (SPM_BASE + 0x014)
29 #define PCM_CON0 (SPM_BASE + 0x018)
30 #define PCM_CON1 (SPM_BASE + 0x01C)
31 #define SPM_POWER_ON_VAL2 (SPM_BASE + 0x020)
32 #define SPM_POWER_ON_VAL3 (SPM_BASE + 0x024)
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spm/
H A Dmt_spm_reg.h20 #define POWERON_CONFIG_EN (SPM_BASE + 0x000)
21 #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004)
22 #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008)
23 #define SPM_CLK_CON (SPM_BASE + 0x00C)
24 #define SPM_CLK_SETTLE (SPM_BASE + 0x010)
25 #define SPM_AP_STANDBY_CON (SPM_BASE + 0x014)
26 #define PCM_CON0 (SPM_BASE + 0x018)
27 #define PCM_CON1 (SPM_BASE + 0x01C)
28 #define SPM_POWER_ON_VAL2 (SPM_BASE + 0x020)
29 #define SPM_POWER_ON_VAL3 (SPM_BASE + 0x024)
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/
H A Dmt_spm_reg.h15 #define POWERON_CONFIG_EN (SPM_BASE + 0x000)
16 #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004)
17 #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008)
18 #define SPM_CLK_CON (SPM_BASE + 0x00C)
19 #define SPM_CLK_SETTLE (SPM_BASE + 0x010)
20 #define SPM_AP_STANDBY_CON (SPM_BASE + 0x014)
21 #define PCM_CON0 (SPM_BASE + 0x018)
22 #define PCM_CON1 (SPM_BASE + 0x01C)
23 #define SPM_POWER_ON_VAL2 (SPM_BASE + 0x020)
24 #define SPM_POWER_ON_VAL3 (SPM_BASE + 0x024)
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8173/drivers/spm/
H A Dspm.h9 #define SPM_POWERON_CONFIG_SET (SPM_BASE + 0x000)
10 #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x010)
11 #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x014)
12 #define SPM_CLK_SETTLE (SPM_BASE + 0x100)
13 #define SPM_CA7_CPU1_PWR_CON (SPM_BASE + 0x218)
14 #define SPM_CA7_CPU2_PWR_CON (SPM_BASE + 0x21c)
15 #define SPM_CA7_CPU3_PWR_CON (SPM_BASE + 0x220)
16 #define SPM_CA7_CPU1_L1_PDN (SPM_BASE + 0x264)
17 #define SPM_CA7_CPU2_L1_PDN (SPM_BASE + 0x26c)
18 #define SPM_CA7_CPU3_L1_PDN (SPM_BASE + 0x274)
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/
H A Dmt_spm_reg.h16 #define POWERON_CONFIG_EN (SPM_BASE + 0x0000)
17 #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x0004)
18 #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x0008)
19 #define SPM_POWER_ON_VAL2 (SPM_BASE + 0x000C)
20 #define SPM_POWER_ON_VAL3 (SPM_BASE + 0x0010)
21 #define PCM_PWR_IO_EN (SPM_BASE + 0x0014)
22 #define PCM_CON0 (SPM_BASE + 0x0018)
23 #define PCM_CON1 (SPM_BASE + 0x001C)
24 #define SPM_SRAM_SLEEP_CTRL (SPM_BASE + 0x0020)
25 #define SPM_CLK_CON (SPM_BASE + 0x0024)
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8183/drivers/spm/
H A Dspm.h14 #define POWERON_CONFIG_EN (SPM_BASE + 0x000)
15 #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004)
16 #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008)
17 #define SPM_CLK_CON (SPM_BASE + 0x00C)
18 #define SPM_CLK_SETTLE (SPM_BASE + 0x010)
19 #define SPM_AP_STANDBY_CON (SPM_BASE + 0x014)
20 #define PCM_CON0 (SPM_BASE + 0x018)
21 #define PCM_CON1 (SPM_BASE + 0x01C)
22 #define PCM_IM_PTR (SPM_BASE + 0x020)
23 #define PCM_IM_LEN (SPM_BASE + 0x024)
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/
H A Dmt_spm_reg.h21 #define POWERON_CONFIG_EN (SPM_BASE + 0x000)
22 #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004)
23 #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008)
24 #define SPM_POWER_ON_VAL2 (SPM_BASE + 0x00C)
25 #define SPM_POWER_ON_VAL3 (SPM_BASE + 0x010)
26 #define PCM_PWR_IO_EN (SPM_BASE + 0x014)
27 #define PCM_CON0 (SPM_BASE + 0x018)
28 #define PCM_CON1 (SPM_BASE + 0x01C)
29 #define SPM_SRAM_SLEEP_CTRL (SPM_BASE + 0x020)
30 #define SPM_CLK_CON (SPM_BASE + 0x024)
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8183/drivers/spmc/
H A Dmtspmc_private.h23 #define SPM_POWERON_CONFIG_EN (SPM_BASE + 0x000)
29 #define SPM_PWR_STATUS (SPM_BASE + 0x180)
30 #define SPM_PWR_STATUS_2ND (SPM_BASE + 0x184)
32 #define SPM_BYPASS_SPMC (SPM_BASE + 0x2b4)
33 #define SPM_SPMC_DORMANT_ENABLE (SPM_BASE + 0x2b8)
35 #define SPM_MP0_CPUTOP_PWR_CON (SPM_BASE + 0x204)
36 #define SPM_MP0_CPU0_PWR_CON (SPM_BASE + 0x208)
37 #define SPM_MP0_CPU1_PWR_CON (SPM_BASE + 0x20C)
38 #define SPM_MP0_CPU2_PWR_CON (SPM_BASE + 0x210)
39 #define SPM_MP0_CPU3_PWR_CON (SPM_BASE + 0x214)
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/mtcmos/mt8196/
H A Dmtcmos.h19 #define POWERON_CONFIG_EN (SPM_BASE + 0x0)
20 #define UFS0_PWR_CON (SPM_BASE + 0xE2C)
21 #define UFS0_PHY_PWR_CON (SPM_BASE + 0xE30)
23 #define SPM_BUS_PROTECT_EN_SET (SPM_BASE + 0x90DC)
24 #define SPM_BUS_PROTECT_EN_CLR (SPM_BASE + 0x90E0)
25 #define SPM_BUS_PROTECT_CG_EN_SET (SPM_BASE + 0x90F4)
26 #define SPM_BUS_PROTECT_CG_EN_CLR (SPM_BASE + 0x90F8)
27 #define SPM_BUS_PROTECT_RDY_STA (SPM_BASE + 0x9208)
/rk3399_ARM-atf/plat/mediatek/mt8196/include/
H A Dplatform_def.h70 #define SPM_BASE (IO_PHYS + 0x0C004000) macro
77 #ifdef SPM_BASE
78 #define SPM_EXT_INT_WAKEUP_REQ (SPM_BASE + 0x210)
79 #define SPM_EXT_INT_WAKEUP_REQ_SET (SPM_BASE + 0x214)
80 #define SPM_EXT_INT_WAKEUP_REQ_CLR (SPM_BASE + 0x218)
81 #define SPM_CPU_BUCK_ISO_CON (SPM_BASE + 0xEF8)
83 #define SPM_AUDIO_PWR_CON (SPM_BASE + 0xE4C)
/rk3399_ARM-atf/plat/mediatek/drivers/mtcmos/mt8189/
H A Dmtcmos.h19 #define POWERON_CONFIG_EN (SPM_BASE + 0x0)
20 #define UFS0_PWR_CON (SPM_BASE + 0x0E10)
21 #define UFS0_PHY_PWR_CON (SPM_BASE + 0x0E14)
/rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv3_2/
H A Dmt_cpu_pm.h41 #define SPM_VLP_MCUSYS_PWR_CON (SPM_BASE + 0x260)
42 #define SPM_VLP_MP0_CPUTOP_PWR_CON (SPM_BASE + 0x264)
43 #define SPM_VLP_CPU_PWR_CON(core) (SPM_BASE + 0x268 + ((core) * 4))
H A Dmt_smp.h14 #define SPM_POWERON_CONFIG_EN (SPM_BASE + 0x000)
/rk3399_ARM-atf/plat/mediatek/mt8186/include/
H A Dplatform_def.h27 #define SPM_BASE (IO_PHYS + 0x00006000) macro
44 #define SPM_BASE (IO_PHYS + 0x00006000) macro
/rk3399_ARM-atf/plat/mediatek/mt8189/include/
H A Dplatform_def.h44 #define SPM_BASE (IO_PHYS + 0x0C001000) macro
265 #define SPM_BASE (IO_PHYS + 0x0C001000) macro
/rk3399_ARM-atf/plat/mediatek/drivers/vcp/rv/
H A Dvcp_common.c45 #if defined(SPM_BASE) in get_vcp_pwr_status()
46 uint32_t spm_pwr_sta = mmio_read_32(SPM_BASE + VCP_POWER_STATUS); in get_vcp_pwr_status()
/rk3399_ARM-atf/plat/mediatek/mt8183/
H A Dplat_dcm.c19 #define PWR_STATUS (SPM_BASE + 0x180)
/rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv5_4/
H A Dmt_cpu_pm.h47 #define SPM_POWERON_CONFIG_EN (SPM_BASE + 0x000)
48 #define SPM_CPU_PWR_STATUS (SPM_BASE + 0x174)
/rk3399_ARM-atf/plat/mediatek/mt8192/include/
H A Dplatform_def.h42 #define SPM_BASE (IO_PHYS + 0x00006000) macro
/rk3399_ARM-atf/plat/mediatek/mt8173/include/
H A Dmt8173_def.h22 #define SPM_BASE (IO_PHYS + 0x6000) macro
/rk3399_ARM-atf/plat/mediatek/mt8195/include/
H A Dplatform_def.h36 #define SPM_BASE (IO_PHYS + 0x00006000) macro
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spmc/
H A Dmtspmc_private.h32 #define SPM_REG(ofs) (uint32_t)(SPM_BASE + (ofs))
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spmc/
H A Dmtspmc_private.h30 #define SPM_REG(ofs) (uint32_t)(SPM_BASE + (ofs))

12