1 /* 2 * Copyright (c) 2022, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MT_CPU_PM_H 8 #define MT_CPU_PM_H 9 10 #include <assert.h> 11 #include <mcucfg.h> 12 #include <platform_def.h> 13 14 /* 15 * After ARM v8.2, the cache will turn off automatically when powering down CPU. Therefore, there 16 * is no doubt to use the spin_lock here. 17 */ 18 #if !HW_ASSISTED_COHERENCY 19 #define MT_CPU_PM_USING_BAKERY_LOCK 20 #endif 21 22 #define CPU_PM_FN (MTK_CPUPM_FN_CPUPM_GET_PWR_STATE | \ 23 MTK_CPUPM_FN_PWR_STATE_VALID | \ 24 MTK_CPUPM_FN_PWR_ON_CORE_PREPARE | \ 25 MTK_CPUPM_FN_RESUME_CORE | \ 26 MTK_CPUPM_FN_SUSPEND_MCUSYS | \ 27 MTK_CPUPM_FN_RESUME_MCUSYS | \ 28 MTK_CPUPM_FN_SMP_INIT | \ 29 MTK_CPUPM_FN_SMP_CORE_ON | \ 30 MTK_CPUPM_FN_SMP_CORE_OFF) 31 32 #define CPU_PM_ASSERT(_cond) ({ \ 33 if (!(_cond)) { \ 34 INFO("[%s:%d] - %s\n", __func__, __LINE__, #_cond); \ 35 panic(); \ 36 } }) 37 38 #define CPC_PWR_MASK_MCUSYS_MP0 (0xC001) 39 40 #ifdef CPU_PM_SPM_CORE_POWERON 41 #define SPM_VLP_MCUSYS_PWR_CON (SPM_BASE + 0x260) 42 #define SPM_VLP_MP0_CPUTOP_PWR_CON (SPM_BASE + 0x264) 43 #define SPM_VLP_CPU_PWR_CON(core) (SPM_BASE + 0x268 + ((core) * 4)) 44 #else 45 #define SPM_VLP_CPU_PWR_CON(core) 0 46 #endif 47 48 #define PER_CPU_PWR_DATA(ctrl, cluster, core) \ 49 do { \ 50 ctrl.rvbaraddr_l = CORE_RVBRADDR_##cluster##_##core##_L; \ 51 ctrl.arch_addr = MCUCFG_MP0_CLUSTER_CFG5; \ 52 ctrl.pwpr = SPM_MP##cluster##_CPU##core##_PWR_CON; \ 53 ctrl.pwpr_intermediate = SPM_VLP_CPU_PWR_CON(core); \ 54 } while (0) 55 56 #define PER_CPU_PWR_CTRL(ctrl, cpu) ({ \ 57 switch (cpu) { \ 58 case 0: \ 59 PER_CPU_PWR_DATA(ctrl, 0, 0); \ 60 break; \ 61 case 1: \ 62 PER_CPU_PWR_DATA(ctrl, 0, 1); \ 63 break; \ 64 case 2: \ 65 PER_CPU_PWR_DATA(ctrl, 0, 2); \ 66 break; \ 67 case 3: \ 68 PER_CPU_PWR_DATA(ctrl, 0, 3); \ 69 break; \ 70 case 4: \ 71 PER_CPU_PWR_DATA(ctrl, 0, 4); \ 72 break; \ 73 case 5: \ 74 PER_CPU_PWR_DATA(ctrl, 0, 5); \ 75 break; \ 76 case 6: \ 77 PER_CPU_PWR_DATA(ctrl, 0, 6); \ 78 break; \ 79 case 7: \ 80 PER_CPU_PWR_DATA(ctrl, 0, 7); \ 81 break; \ 82 default: \ 83 PER_CPU_PWR_DATA(ctrl, 0, 0); \ 84 assert(0); \ 85 break; \ 86 } }) 87 88 89 /* MCUSYS DREQ BIG VPROC ISO control */ 90 #define DREQ20_BIG_VPROC_ISO (MCUCFG_BASE + 0xad8c) 91 92 /* Definition about bootup address for each core CORE_RVBRADDR_clusterid_cpuid */ 93 #define CORE_RVBRADDR_0_0_L (MCUCFG_BASE + 0xc900) 94 #define CORE_RVBRADDR_0_1_L (MCUCFG_BASE + 0xc908) 95 #define CORE_RVBRADDR_0_2_L (MCUCFG_BASE + 0xc910) 96 #define CORE_RVBRADDR_0_3_L (MCUCFG_BASE + 0xc918) 97 #define CORE_RVBRADDR_0_4_L (MCUCFG_BASE + 0xc920) 98 #define CORE_RVBRADDR_0_5_L (MCUCFG_BASE + 0xc928) 99 #define CORE_RVBRADDR_0_6_L (MCUCFG_BASE + 0xc930) 100 #define CORE_RVBRADDR_0_7_L (MCUCFG_BASE + 0xc938) 101 #define MCUCFG_MP0_CLUSTER_CFG5 (MCUCFG_BASE + 0xc8e4) 102 103 struct cpu_pwr_ctrl { 104 unsigned int rvbaraddr_l; 105 unsigned int arch_addr; 106 unsigned int pwpr; 107 unsigned int pwpr_intermediate; 108 }; 109 110 #define MCUSYS_STATUS_PDN BIT(0) 111 #define MCUSYS_STATUS_CPUSYS_PROTECT BIT(8) 112 #define MCUSYS_STATUS_MCUSYS_PROTECT BIT(9) 113 114 /* cpu_pm function ID */ 115 enum mt_cpu_pm_user_id { 116 MCUSYS_STATUS, 117 CPC_COMMAND, 118 }; 119 120 /* cpu_pm lp function ID */ 121 enum mt_cpu_pm_lp_smc_id { 122 LP_CPC_COMMAND, 123 IRQS_REMAIN_ALLOC, 124 IRQS_REMAIN_CTRL, 125 IRQS_REMAIN_IRQ, 126 IRQS_REMAIN_WAKEUP_CAT, 127 IRQS_REMAIN_WAKEUP_SRC, 128 }; 129 130 #endif /* MT_CPU_PM_H */ 131