141004253Sirving-ch-lin /* 241004253Sirving-ch-lin * Copyright (c) 2025, MediaTek Inc. All rights reserved. 341004253Sirving-ch-lin * 441004253Sirving-ch-lin * SPDX-License-Identifier: BSD-3-Clause 541004253Sirving-ch-lin */ 641004253Sirving-ch-lin 741004253Sirving-ch-lin #ifndef PLAT_MEDIATEK_DRIVERS_MTCMOS_MT8196_MTCMOS_H_ 841004253Sirving-ch-lin #define PLAT_MEDIATEK_DRIVERS_MTCMOS_MT8196_MTCMOS_H_ 941004253Sirving-ch-lin 10*68514bd9Sirving-ch-lin #include <lib/utils_def.h> 1141004253Sirving-ch-lin #include <mtcmos_common.h> 1241004253Sirving-ch-lin #include <platform_def.h> 1341004253Sirving-ch-lin 1441004253Sirving-ch-lin #define RTFF_SAVE BIT(24) 1541004253Sirving-ch-lin #define RTFF_NRESTORE BIT(25) 1641004253Sirving-ch-lin #define RTFF_CLK_DIS BIT(26) 1741004253Sirving-ch-lin #define RTFF_SAVE_FLAG BIT(27) 1841004253Sirving-ch-lin 1941004253Sirving-ch-lin #define POWERON_CONFIG_EN (SPM_BASE + 0x0) 2041004253Sirving-ch-lin #define UFS0_PWR_CON (SPM_BASE + 0xE2C) 2141004253Sirving-ch-lin #define UFS0_PHY_PWR_CON (SPM_BASE + 0xE30) 2241004253Sirving-ch-lin 2341004253Sirving-ch-lin #define SPM_BUS_PROTECT_EN_SET (SPM_BASE + 0x90DC) 2441004253Sirving-ch-lin #define SPM_BUS_PROTECT_EN_CLR (SPM_BASE + 0x90E0) 2541004253Sirving-ch-lin #define SPM_BUS_PROTECT_CG_EN_SET (SPM_BASE + 0x90F4) 2641004253Sirving-ch-lin #define SPM_BUS_PROTECT_CG_EN_CLR (SPM_BASE + 0x90F8) 2741004253Sirving-ch-lin #define SPM_BUS_PROTECT_RDY_STA (SPM_BASE + 0x9208) 2841004253Sirving-ch-lin 2941004253Sirving-ch-lin #define UFS0_PROT_STEP1_MASK BIT(11) 3041004253Sirving-ch-lin #define UFS0_PHY_PROT_STEP1_MASK BIT(12) 3141004253Sirving-ch-lin 3241004253Sirving-ch-lin static const struct bus_protect ufs0_bus_prot_set_table[] = { 3341004253Sirving-ch-lin {SPM_BUS_PROTECT_CG_EN_SET, 0x0, UFS0_PROT_STEP1_MASK}, 3441004253Sirving-ch-lin {SPM_BUS_PROTECT_EN_SET, SPM_BUS_PROTECT_RDY_STA, UFS0_PROT_STEP1_MASK}, 3541004253Sirving-ch-lin {SPM_BUS_PROTECT_CG_EN_CLR, 0x0, UFS0_PROT_STEP1_MASK}, 3641004253Sirving-ch-lin }; 3741004253Sirving-ch-lin 3841004253Sirving-ch-lin static const struct bus_protect ufs0_bus_prot_clr_table[] = { 3941004253Sirving-ch-lin {SPM_BUS_PROTECT_CG_EN_SET, 0x0, UFS0_PROT_STEP1_MASK}, 4041004253Sirving-ch-lin {SPM_BUS_PROTECT_EN_CLR, 0x0, UFS0_PROT_STEP1_MASK}, 4141004253Sirving-ch-lin {SPM_BUS_PROTECT_CG_EN_CLR, 0x0, UFS0_PROT_STEP1_MASK}, 4241004253Sirving-ch-lin }; 4341004253Sirving-ch-lin 4441004253Sirving-ch-lin static const struct bus_protect ufs0_phy_bus_prot_set_table[] = { 4541004253Sirving-ch-lin {SPM_BUS_PROTECT_CG_EN_SET, 0x0, UFS0_PHY_PROT_STEP1_MASK}, 4641004253Sirving-ch-lin {SPM_BUS_PROTECT_EN_SET, SPM_BUS_PROTECT_RDY_STA, UFS0_PHY_PROT_STEP1_MASK}, 4741004253Sirving-ch-lin {SPM_BUS_PROTECT_CG_EN_CLR, 0x0, UFS0_PHY_PROT_STEP1_MASK}, 4841004253Sirving-ch-lin }; 4941004253Sirving-ch-lin 5041004253Sirving-ch-lin static const struct bus_protect ufs0_phy_bus_prot_clr_table[] = { 5141004253Sirving-ch-lin {SPM_BUS_PROTECT_CG_EN_SET, 0x0, UFS0_PHY_PROT_STEP1_MASK}, 5241004253Sirving-ch-lin {SPM_BUS_PROTECT_EN_CLR, 0x0, UFS0_PHY_PROT_STEP1_MASK}, 5341004253Sirving-ch-lin {SPM_BUS_PROTECT_CG_EN_CLR, 0x0, UFS0_PHY_PROT_STEP1_MASK}, 5441004253Sirving-ch-lin }; 5541004253Sirving-ch-lin 5641004253Sirving-ch-lin #endif /* PLAT_MEDIATEK_DRIVERS_MTCMOS_MT8196_MTCMOS_H_ */ 57