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Searched refs:PLAT_MAX_RET_STATE (Results 1 – 25 of 109) sorted by relevance

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/rk3399_ARM-atf/plat/nxp/common/psci/
H A Dplat_psci.c151 if (cpu_state == PLAT_MAX_RET_STATE) { in _pwr_cpu_standby()
184 == PLAT_MAX_RET_STATE) { in _pwr_suspend()
206 PLAT_MAX_RET_STATE) { in _pwr_suspend()
227 else if (state->pwr_domain_state[PLAT_CORE_LVL] == PLAT_MAX_RET_STATE) { in _pwr_suspend()
259 == PLAT_MAX_RET_STATE) { in _pwr_suspend_finish()
285 PLAT_MAX_RET_STATE) { in _pwr_suspend_finish()
309 else if (state->pwr_domain_state[PLAT_CORE_LVL] == PLAT_MAX_RET_STATE) { in _pwr_suspend_finish()
352 PLAT_MAX_RET_STATE; in _pwr_state_validate()
360 PLAT_MAX_RET_STATE; in _pwr_state_validate()
368 PLAT_MAX_RET_STATE; in _pwr_state_validate()
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/rk3399_ARM-atf/plat/nxp/soc-ls1028a/include/
H A Dsoc.h128 #define PLAT_MAX_RET_STATE (PSCI_LOCAL_STATE_RUN + 1) macro
129 #define LS_LOCAL_STATE_RET PLAT_MAX_RET_STATE
132 #define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1)
/rk3399_ARM-atf/plat/imx/imx8m/imx8mq/
H A Dimx8mq_psci.c32 CORE_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; in imx_validate_power_state()
33 CLUSTER_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; in imx_validate_power_state()
38 CLUSTER_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; in imx_validate_power_state()
128 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PLAT_MAX_RET_STATE; in imx_get_sys_suspend_power_state()
/rk3399_ARM-atf/plat/imx/imx93/
H A Dimx93_psci.c50 CORE_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; in imx_validate_power_state()
51 CLUSTER_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; in imx_validate_power_state()
56 CLUSTER_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; in imx_validate_power_state()
199 SYSTEM_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; in imx_get_sys_suspend_power_state()
200 CLUSTER_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; in imx_get_sys_suspend_power_state()
/rk3399_ARM-atf/plat/nxp/soc-ls1088a/include/
H A Dsoc.h210 #define PLAT_MAX_RET_STATE (PSCI_LOCAL_STATE_RUN + 1) macro
211 #define LS_LOCAL_STATE_RET PLAT_MAX_RET_STATE
214 #define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1)
/rk3399_ARM-atf/plat/xilinx/versal/
H A Dplat_psci.c85 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in versal_pwr_domain_suspend()
89 state = (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) ? in versal_pwr_domain_suspend()
97 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in versal_pwr_domain_suspend()
131 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in versal_pwr_domain_suspend_finish()
287 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in versal_validate_power_state()
/rk3399_ARM-atf/plat/imx/common/
H A Dimx8_psci.c45 req_state->pwr_domain_state[MPIDR_AFFLVL1] = PLAT_MAX_RET_STATE; in imx_validate_power_state()
60 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PLAT_MAX_RET_STATE; in imx_get_sys_suspend_power_state()
/rk3399_ARM-atf/plat/nxp/soc-ls1043a/include/
H A Dsoc.h206 #define PLAT_MAX_RET_STATE (PSCI_LOCAL_STATE_RUN + 1) macro
207 #define LS_LOCAL_STATE_RET PLAT_MAX_RET_STATE
210 #define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1)
/rk3399_ARM-atf/plat/nxp/soc-ls1046a/include/
H A Dsoc.h98 #define PLAT_MAX_RET_STATE (PSCI_LOCAL_STATE_RUN + 1) macro
101 #define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1)
/rk3399_ARM-atf/plat/xilinx/zynqmp/
H A Dplat_psci.c115 state = (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) ? in zynqmp_pwr_domain_suspend()
123 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in zynqmp_pwr_domain_suspend()
159 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in zynqmp_pwr_domain_suspend_finish()
225 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in zynqmp_validate_power_state()
/rk3399_ARM-atf/plat/nxp/soc-lx2160a/include/
H A Dsoc.h129 #define PLAT_MAX_RET_STATE (PSCI_LOCAL_STATE_RUN + 1) macro
132 #define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1)
/rk3399_ARM-atf/plat/xilinx/versal_net/
H A Dplat_psci_pm.c226 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in versal_net_pwr_domain_suspend()
230 state = (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) ? in versal_net_pwr_domain_suspend()
274 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in versal_net_pwr_domain_suspend_finish()
320 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in versal_net_validate_power_state()
/rk3399_ARM-atf/plat/amd/versal2/
H A Dplat_psci_pm.c175 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in versal2_pwr_domain_suspend()
179 state = (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) ? in versal2_pwr_domain_suspend()
259 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in versal2_pwr_domain_suspend_finish()
326 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in versal2_validate_power_state()
/rk3399_ARM-atf/plat/mediatek/include/armv8_2/
H A Darch_def.h12 #define PLAT_MAX_RET_STATE (1) macro
/rk3399_ARM-atf/plat/mediatek/lib/pm/
H A Dmtk_pm.h214 #define PLAT_MT_CPU_SUSPEND_CLUSTER PLAT_MAX_RET_STATE
215 #define PLAT_MT_CPU_SUSPEND_MCUSYS PLAT_MAX_RET_STATE
218 #define IS_PLAT_SYSTEM_RETENTION(aff) (aff >= PLAT_MAX_RET_STATE)
/rk3399_ARM-atf/plat/mediatek/include/armv9/
H A Darch_def.h16 #define PLAT_MAX_RET_STATE MPIDR_AFFLVL1 macro
/rk3399_ARM-atf/plat/mediatek/mt8186/include/
H A Dplat_pm.h116 #define PLAT_MT_CPU_SUSPEND_CLUSTER PLAT_MAX_RET_STATE
119 #define IS_PLAT_SYSTEM_RETENTION(aff) (aff >= PLAT_MAX_RET_STATE)
/rk3399_ARM-atf/plat/hisilicon/hikey/include/
H A Dplatform_def.h39 #define PLAT_MAX_RET_STATE U(1) macro
/rk3399_ARM-atf/plat/amlogic/gxl/include/
H A Dplatform_def.h31 #define PLAT_MAX_RET_STATE U(1) macro
/rk3399_ARM-atf/plat/amlogic/g12a/include/
H A Dplatform_def.h31 #define PLAT_MAX_RET_STATE U(1) macro
/rk3399_ARM-atf/plat/amlogic/gxbb/include/
H A Dplatform_def.h34 #define PLAT_MAX_RET_STATE U(1) macro
/rk3399_ARM-atf/plat/amlogic/axg/include/
H A Dplatform_def.h31 #define PLAT_MAX_RET_STATE U(1) macro
/rk3399_ARM-atf/plat/mediatek/include/lib/pm/
H A Dmtk_pm.h308 #define PLAT_MT_CPU_SUSPEND_CLUSTER PLAT_MAX_RET_STATE
314 #define PLAT_MT_CPU_SUSPEND_MCUSYS PLAT_MAX_RET_STATE
318 #define IS_PLAT_SYSTEM_RETENTION(aff) ((aff) >= PLAT_MAX_RET_STATE)
/rk3399_ARM-atf/plat/rockchip/common/
H A Dplat_pm.c152 PLAT_MAX_RET_STATE; in rockchip_validate_power_state()
160 PLAT_MAX_RET_STATE; in rockchip_validate_power_state()
185 assert(cpu_state == PLAT_MAX_RET_STATE); in rockchip_cpu_standby()
/rk3399_ARM-atf/plat/imx/imx8m/imx8mq/include/
H A Dplatform_def.h30 #define PLAT_MAX_RET_STATE U(1) macro
32 #define PLAT_WAIT_RET_STATE PLAT_MAX_RET_STATE

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