xref: /rk3399_ARM-atf/plat/amlogic/axg/include/platform_def.h (revision 4811168aafc8bdb5869d26744fa8636752b5ca32)
1afd241e7SCarlo Caione /*
2*47f2445aSAlexei Fedorov  * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved.
3afd241e7SCarlo Caione  *
4afd241e7SCarlo Caione  * SPDX-License-Identifier: BSD-3-Clause
5afd241e7SCarlo Caione  */
6afd241e7SCarlo Caione 
7afd241e7SCarlo Caione #ifndef PLATFORM_DEF_H
8afd241e7SCarlo Caione #define PLATFORM_DEF_H
9afd241e7SCarlo Caione 
10afd241e7SCarlo Caione #include <arch.h>
11afd241e7SCarlo Caione #include <lib/utils_def.h>
12afd241e7SCarlo Caione 
13afd241e7SCarlo Caione #include "../axg_def.h"
14afd241e7SCarlo Caione 
15afd241e7SCarlo Caione #define PLATFORM_LINKER_FORMAT		"elf64-littleaarch64"
16afd241e7SCarlo Caione #define PLATFORM_LINKER_ARCH		aarch64
17afd241e7SCarlo Caione 
18afd241e7SCarlo Caione #define PLATFORM_STACK_SIZE		UL(0x1000)
19afd241e7SCarlo Caione 
20afd241e7SCarlo Caione #define PLATFORM_MAX_CPUS_PER_CLUSTER	U(4)
21afd241e7SCarlo Caione #define PLATFORM_CLUSTER_COUNT		U(1)
22afd241e7SCarlo Caione #define PLATFORM_CLUSTER0_CORE_COUNT	PLATFORM_MAX_CPUS_PER_CLUSTER
23afd241e7SCarlo Caione #define PLATFORM_CORE_COUNT		PLATFORM_CLUSTER0_CORE_COUNT
24afd241e7SCarlo Caione 
25afd241e7SCarlo Caione #define AML_PRIMARY_CPU			U(0)
26afd241e7SCarlo Caione 
27*47f2445aSAlexei Fedorov #define PLAT_MAX_PWR_LVL		MPIDR_AFFLVL2
28afd241e7SCarlo Caione #define PLAT_NUM_PWR_DOMAINS		(PLATFORM_CLUSTER_COUNT + \
29afd241e7SCarlo Caione 					 PLATFORM_CORE_COUNT)
30afd241e7SCarlo Caione 
31afd241e7SCarlo Caione #define PLAT_MAX_RET_STATE		U(1)
32afd241e7SCarlo Caione #define PLAT_MAX_OFF_STATE		U(2)
33afd241e7SCarlo Caione 
34afd241e7SCarlo Caione #define PLAT_SYS_CPU_CFG7		(U(1) << 25)
35afd241e7SCarlo Caione #define PLAT_AO_TIMESTAMP_CNTL		U(0x1ff)
36afd241e7SCarlo Caione 
37afd241e7SCarlo Caione /* Local power state for power domains in Run state. */
38afd241e7SCarlo Caione #define PLAT_LOCAL_STATE_RUN		U(0)
39afd241e7SCarlo Caione /* Local power state for retention. Valid only for CPU power domains */
40afd241e7SCarlo Caione #define PLAT_LOCAL_STATE_RET		U(1)
41afd241e7SCarlo Caione /* Local power state for power-down. Valid for CPU and cluster power domains. */
42afd241e7SCarlo Caione #define PLAT_LOCAL_STATE_OFF		U(2)
43afd241e7SCarlo Caione 
44afd241e7SCarlo Caione /*
45afd241e7SCarlo Caione  * Macros used to parse state information from State-ID if it is using the
46afd241e7SCarlo Caione  * recommended encoding for State-ID.
47afd241e7SCarlo Caione  */
48afd241e7SCarlo Caione #define PLAT_LOCAL_PSTATE_WIDTH		U(4)
49afd241e7SCarlo Caione #define PLAT_LOCAL_PSTATE_MASK		((U(1) << PLAT_LOCAL_PSTATE_WIDTH) - 1)
50afd241e7SCarlo Caione 
51afd241e7SCarlo Caione /*
52afd241e7SCarlo Caione  * Some data must be aligned on the biggest cache line size in the platform.
53afd241e7SCarlo Caione  * This is known only to the platform as it might have a combination of
54afd241e7SCarlo Caione  * integrated and external caches.
55afd241e7SCarlo Caione  */
56afd241e7SCarlo Caione #define CACHE_WRITEBACK_SHIFT		U(6)
57afd241e7SCarlo Caione #define CACHE_WRITEBACK_GRANULE		(U(1) << CACHE_WRITEBACK_SHIFT)
58afd241e7SCarlo Caione 
59afd241e7SCarlo Caione /* Memory-related defines */
60afd241e7SCarlo Caione #define PLAT_PHY_ADDR_SPACE_SIZE	(ULL(1) << 32)
61afd241e7SCarlo Caione #define PLAT_VIRT_ADDR_SPACE_SIZE	(ULL(1) << 32)
62afd241e7SCarlo Caione 
63afd241e7SCarlo Caione #define MAX_MMAP_REGIONS		16
64afd241e7SCarlo Caione #define MAX_XLAT_TABLES			8
65afd241e7SCarlo Caione 
66afd241e7SCarlo Caione #endif /* PLATFORM_DEF_H */
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