1*a65fadfbSGavin Liu /* 2*a65fadfbSGavin Liu * Copyright (c) 2024, Mediatek Inc. All rights reserved. 3*a65fadfbSGavin Liu * 4*a65fadfbSGavin Liu * SPDX-License-Identifier: BSD-3-Clause 5*a65fadfbSGavin Liu */ 6*a65fadfbSGavin Liu 7*a65fadfbSGavin Liu #ifndef ARCH_DEF_H 8*a65fadfbSGavin Liu #define ARCH_DEF_H 9*a65fadfbSGavin Liu 10*a65fadfbSGavin Liu #include <arch.h> 11*a65fadfbSGavin Liu 12*a65fadfbSGavin Liu /* Topology constants */ 13*a65fadfbSGavin Liu #ifndef PLAT_MAX_PWR_LVL 14*a65fadfbSGavin Liu #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 15*a65fadfbSGavin Liu #endif 16*a65fadfbSGavin Liu #define PLAT_MAX_RET_STATE MPIDR_AFFLVL1 17*a65fadfbSGavin Liu 18*a65fadfbSGavin Liu #ifndef PLAT_MAX_OFF_STATE 19*a65fadfbSGavin Liu #define PLAT_MAX_OFF_STATE MPIDR_AFFLVL2 20*a65fadfbSGavin Liu #endif 21*a65fadfbSGavin Liu 22*a65fadfbSGavin Liu #define PLATFORM_SYSTEM_COUNT 1 23*a65fadfbSGavin Liu #define PLATFORM_CLUSTER_COUNT 1 24*a65fadfbSGavin Liu #define PLATFORM_CLUSTER0_CORE_COUNT 8 25*a65fadfbSGavin Liu #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) 26*a65fadfbSGavin Liu #define PLATFORM_MAX_CPUS_PER_CLUSTER 8 27*a65fadfbSGavin Liu #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ 28*a65fadfbSGavin Liu PLATFORM_CLUSTER_COUNT + \ 29*a65fadfbSGavin Liu PLATFORM_CORE_COUNT) 30*a65fadfbSGavin Liu 31*a65fadfbSGavin Liu /* Cachline size */ 32*a65fadfbSGavin Liu #define CACHE_WRITEBACK_SHIFT 6 33*a65fadfbSGavin Liu #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 34*a65fadfbSGavin Liu #endif /* ARCH_DEF_H */ 35