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Searched refs:PLAT_GICR_BASE (Results 1 – 23 of 23) sorted by relevance

/rk3399_ARM-atf/plat/imx/common/
H A Dplat_imx8_gic.c43 .gicr_base = PLAT_GICR_BASE,
66 unsigned int val = mmio_read_32(PLAT_GICR_BASE + GICR_WAKER); in plat_gicr_exit_sleep()
75 mmio_write_32(PLAT_GICR_BASE + GICR_WAKER, val & ~WAKER_SL_BIT); in plat_gicr_exit_sleep()
77 while ((mmio_read_32(PLAT_GICR_BASE + GICR_WAKER) & WAKER_QSC_BIT) != 0U) in plat_gicr_exit_sleep()
/rk3399_ARM-atf/plat/intel/soc/agilex5/include/
H A Dsocfpga_plat_def.h168 #define PLAT_GICR_BASE (PLAT_GIC_BASE + 0x60000) macro
170 #define PLAT_INTEL_SOCFPGA_GICR_BASE PLAT_GICR_BASE
/rk3399_ARM-atf/plat/imx/imx9/imx95/include/
H A Dplatform_def.h44 #define PLAT_GICR_BASE U(0x48060000) macro
45 #define PLAT_ARM_GICR_BASE PLAT_GICR_BASE
/rk3399_ARM-atf/plat/imx/imx9/imx94/include/
H A Dplatform_def.h42 #define PLAT_GICR_BASE U(0x48060000) macro
43 #define PLAT_ARM_GICR_BASE PLAT_GICR_BASE
/rk3399_ARM-atf/plat/imx/imx8qx/include/
H A Dplatform_def.h40 #define PLAT_GICR_BASE 0x51b00000 macro
/rk3399_ARM-atf/plat/rockchip/rk3576/include/
H A Dplatform_def.h109 #define PLAT_RK_GICR_BASE PLAT_GICR_BASE
/rk3399_ARM-atf/plat/imx/imx8qm/include/
H A Dplatform_def.h39 #define PLAT_GICR_BASE 0x51b00000 macro
/rk3399_ARM-atf/plat/rockchip/rk3588/include/
H A Dplatform_def.h111 #define PLAT_RK_GICR_BASE PLAT_GICR_BASE
/rk3399_ARM-atf/plat/intel/soc/stratix10/include/
H A Dsocfpga_plat_def.h102 #define PLAT_GICR_BASE 0 macro
/rk3399_ARM-atf/plat/intel/soc/n5x/include/
H A Dsocfpga_plat_def.h102 #define PLAT_GICR_BASE 0 macro
/rk3399_ARM-atf/plat/rockchip/rk3568/include/
H A Dplatform_def.h111 #define PLAT_RK_GICR_BASE PLAT_GICR_BASE
/rk3399_ARM-atf/plat/nxp/s32/s32g274ardb2/include/
H A Dplatform_def.h78 #define PLAT_GICR_BASE (S32G_GIC_BASE + UL(0x80000)) macro
/rk3399_ARM-atf/plat/intel/soc/agilex/include/
H A Dsocfpga_plat_def.h118 #define PLAT_GICR_BASE 0 macro
/rk3399_ARM-atf/plat/rockchip/rk3568/
H A Drk3568_def.h88 #define PLAT_GICR_BASE (GIC600_BASE + 0x60000) macro
/rk3399_ARM-atf/plat/nxp/s32/s32g274ardb2/
H A Dplat_bl31_setup.c85 .gicr_base = PLAT_GICR_BASE, in bl31_platform_setup()
/rk3399_ARM-atf/plat/imx/imx93/include/
H A Dplatform_def.h44 #define PLAT_GICR_BASE U(0x48040000) macro
/rk3399_ARM-atf/plat/imx/imx8ulp/include/
H A Dplatform_def.h55 #define PLAT_GICR_BASE U(0x2d440000) macro
/rk3399_ARM-atf/plat/rockchip/rk3588/
H A Drk3588_def.h188 #define PLAT_GICR_BASE (GIC600_BASE + 0x80000) macro
/rk3399_ARM-atf/plat/imx/imx8m/imx8mq/include/
H A Dplatform_def.h54 #define PLAT_GICR_BASE U(0x38880000) macro
/rk3399_ARM-atf/plat/rockchip/rk3576/
H A Drk3576_def.h200 #define PLAT_GICR_BASE 0 macro
/rk3399_ARM-atf/plat/imx/imx8m/imx8mm/include/
H A Dplatform_def.h72 #define PLAT_GICR_BASE U(0x38880000) macro
/rk3399_ARM-atf/plat/imx/imx8m/imx8mn/include/
H A Dplatform_def.h56 #define PLAT_GICR_BASE U(0x38880000) macro
/rk3399_ARM-atf/plat/imx/imx8m/imx8mp/include/
H A Dplatform_def.h74 #define PLAT_GICR_BASE U(0x38880000) macro