1*036935a8SXiaoDong Huang /* SPDX-License-Identifier: BSD-3-Clause */ 2*036935a8SXiaoDong Huang /* 3*036935a8SXiaoDong Huang * Copyright (c) 2025, Rockchip Electronics Co., Ltd. 4*036935a8SXiaoDong Huang */ 5*036935a8SXiaoDong Huang 6*036935a8SXiaoDong Huang #ifndef __PLATFORM_DEF_H__ 7*036935a8SXiaoDong Huang #define __PLATFORM_DEF_H__ 8*036935a8SXiaoDong Huang 9*036935a8SXiaoDong Huang #include <arch.h> 10*036935a8SXiaoDong Huang #include <common_def.h> 11*036935a8SXiaoDong Huang #include <rk3576_def.h> 12*036935a8SXiaoDong Huang 13*036935a8SXiaoDong Huang #define DEBUG_XLAT_TABLE 0 14*036935a8SXiaoDong Huang 15*036935a8SXiaoDong Huang /******************************************************************************* 16*036935a8SXiaoDong Huang * Platform binary types for linking 17*036935a8SXiaoDong Huang ******************************************************************************/ 18*036935a8SXiaoDong Huang #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 19*036935a8SXiaoDong Huang #define PLATFORM_LINKER_ARCH aarch64 20*036935a8SXiaoDong Huang 21*036935a8SXiaoDong Huang /******************************************************************************* 22*036935a8SXiaoDong Huang * Generic platform constants 23*036935a8SXiaoDong Huang ******************************************************************************/ 24*036935a8SXiaoDong Huang 25*036935a8SXiaoDong Huang /* Size of cacheable stacks */ 26*036935a8SXiaoDong Huang #if DEBUG_XLAT_TABLE 27*036935a8SXiaoDong Huang #define PLATFORM_STACK_SIZE 0x800 28*036935a8SXiaoDong Huang #elif IMAGE_BL1 29*036935a8SXiaoDong Huang #define PLATFORM_STACK_SIZE 0x440 30*036935a8SXiaoDong Huang #elif IMAGE_BL2 31*036935a8SXiaoDong Huang #define PLATFORM_STACK_SIZE 0x400 32*036935a8SXiaoDong Huang #elif IMAGE_BL31 33*036935a8SXiaoDong Huang #define PLATFORM_STACK_SIZE 0x800 34*036935a8SXiaoDong Huang #elif IMAGE_BL32 35*036935a8SXiaoDong Huang #define PLATFORM_STACK_SIZE 0x440 36*036935a8SXiaoDong Huang #endif 37*036935a8SXiaoDong Huang 38*036935a8SXiaoDong Huang #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 39*036935a8SXiaoDong Huang 40*036935a8SXiaoDong Huang #define PLATFORM_SYSTEM_COUNT 1 41*036935a8SXiaoDong Huang #define PLATFORM_CLUSTER_COUNT 2 42*036935a8SXiaoDong Huang #define PLATFORM_CLUSTER0_CORE_COUNT 4 43*036935a8SXiaoDong Huang #define PLATFORM_CLUSTER1_CORE_COUNT 4 44*036935a8SXiaoDong Huang #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 45*036935a8SXiaoDong Huang PLATFORM_CLUSTER0_CORE_COUNT) 46*036935a8SXiaoDong Huang 47*036935a8SXiaoDong Huang #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ 48*036935a8SXiaoDong Huang PLATFORM_CLUSTER_COUNT + \ 49*036935a8SXiaoDong Huang PLATFORM_CORE_COUNT) 50*036935a8SXiaoDong Huang 51*036935a8SXiaoDong Huang #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 52*036935a8SXiaoDong Huang 53*036935a8SXiaoDong Huang #define PLAT_RK_CLST_TO_CPUID_SHIFT 6 54*036935a8SXiaoDong Huang 55*036935a8SXiaoDong Huang /* 56*036935a8SXiaoDong Huang * This macro defines the deepest retention state possible. A higher state 57*036935a8SXiaoDong Huang * id will represent an invalid or a power down state. 58*036935a8SXiaoDong Huang */ 59*036935a8SXiaoDong Huang #define PLAT_MAX_RET_STATE 1 60*036935a8SXiaoDong Huang 61*036935a8SXiaoDong Huang /* 62*036935a8SXiaoDong Huang * This macro defines the deepest power down states possible. Any state ID 63*036935a8SXiaoDong Huang * higher than this is invalid. 64*036935a8SXiaoDong Huang */ 65*036935a8SXiaoDong Huang #define PLAT_MAX_OFF_STATE 2 66*036935a8SXiaoDong Huang /******************************************************************************* 67*036935a8SXiaoDong Huang * Platform memory map related constants 68*036935a8SXiaoDong Huang ******************************************************************************/ 69*036935a8SXiaoDong Huang /* TF txet, ro, rw, Size: 512KB */ 70*036935a8SXiaoDong Huang #define TZRAM_BASE RK_DRAM_BASE 71*036935a8SXiaoDong Huang #define TZRAM_SIZE 0x100000 72*036935a8SXiaoDong Huang 73*036935a8SXiaoDong Huang /******************************************************************************* 74*036935a8SXiaoDong Huang * BL31 specific defines. 75*036935a8SXiaoDong Huang ******************************************************************************/ 76*036935a8SXiaoDong Huang /* 77*036935a8SXiaoDong Huang * Put BL3-1 at the top of the Trusted RAM 78*036935a8SXiaoDong Huang */ 79*036935a8SXiaoDong Huang #define BL31_BASE (TZRAM_BASE + 0x40000) 80*036935a8SXiaoDong Huang #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 81*036935a8SXiaoDong Huang 82*036935a8SXiaoDong Huang /******************************************************************************* 83*036935a8SXiaoDong Huang * Platform specific page table and MMU setup constants 84*036935a8SXiaoDong Huang ******************************************************************************/ 85*036935a8SXiaoDong Huang #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 86*036935a8SXiaoDong Huang #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 87*036935a8SXiaoDong Huang 88*036935a8SXiaoDong Huang #define ADDR_SPACE_SIZE (1ULL << 32) 89*036935a8SXiaoDong Huang #define MAX_XLAT_TABLES 18 90*036935a8SXiaoDong Huang #define MAX_MMAP_REGIONS 27 91*036935a8SXiaoDong Huang 92*036935a8SXiaoDong Huang /******************************************************************************* 93*036935a8SXiaoDong Huang * Declarations and constants to access the mailboxes safely. Each mailbox is 94*036935a8SXiaoDong Huang * aligned on the biggest cache line size in the platform. This is known only 95*036935a8SXiaoDong Huang * to the platform as it might have a combination of integrated and external 96*036935a8SXiaoDong Huang * caches. Such alignment ensures that two maiboxes do not sit on the same cache 97*036935a8SXiaoDong Huang * line at any cache level. They could belong to different cpus/clusters & 98*036935a8SXiaoDong Huang * get written while being protected by different locks causing corruption of 99*036935a8SXiaoDong Huang * a valid mailbox address. 100*036935a8SXiaoDong Huang ******************************************************************************/ 101*036935a8SXiaoDong Huang #define CACHE_WRITEBACK_SHIFT 6 102*036935a8SXiaoDong Huang #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 103*036935a8SXiaoDong Huang 104*036935a8SXiaoDong Huang /* 105*036935a8SXiaoDong Huang * Define GICD and GICC and GICR base 106*036935a8SXiaoDong Huang */ 107*036935a8SXiaoDong Huang #define PLAT_RK_GICD_BASE PLAT_GICD_BASE 108*036935a8SXiaoDong Huang #define PLAT_RK_GICC_BASE PLAT_GICC_BASE 109*036935a8SXiaoDong Huang #define PLAT_RK_GICR_BASE PLAT_GICR_BASE 110*036935a8SXiaoDong Huang 111*036935a8SXiaoDong Huang #define PLAT_RK_UART_BASE RK_DBG_UART_BASE 112*036935a8SXiaoDong Huang #define PLAT_RK_UART_CLOCK RK_DBG_UART_CLOCK 113*036935a8SXiaoDong Huang #define PLAT_RK_UART_BAUDRATE RK_DBG_UART_BAUDRATE 114*036935a8SXiaoDong Huang 115*036935a8SXiaoDong Huang #define PLAT_RK_PRIMARY_CPU 0x0 116*036935a8SXiaoDong Huang #endif /* __PLATFORM_DEF_H__ */ 117