10bc18309SAnson Huang /* 27a57188bSDeepika Bhavnani * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 30bc18309SAnson Huang * 40bc18309SAnson Huang * SPDX-License-Identifier: BSD-3-Clause 50bc18309SAnson Huang */ 60bc18309SAnson Huang 71083b2b3SAntonio Nino Diaz #ifndef PLATFORM_DEF_H 81083b2b3SAntonio Nino Diaz #define PLATFORM_DEF_H 91083b2b3SAntonio Nino Diaz 1009d40e0eSAntonio Nino Diaz #include <lib/utils_def.h> 110bc18309SAnson Huang 120bc18309SAnson Huang #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 130bc18309SAnson Huang #define PLATFORM_LINKER_ARCH aarch64 140bc18309SAnson Huang 150bc18309SAnson Huang #define PLATFORM_STACK_SIZE 0x400 160bc18309SAnson Huang #define CACHE_WRITEBACK_GRANULE 64 170bc18309SAnson Huang 187a57188bSDeepika Bhavnani #define PLAT_PRIMARY_CPU U(0x0) 197a57188bSDeepika Bhavnani #define PLATFORM_MAX_CPU_PER_CLUSTER U(4) 207a57188bSDeepika Bhavnani #define PLATFORM_CLUSTER_COUNT U(1) 217a57188bSDeepika Bhavnani #define PLATFORM_CORE_COUNT U(4) 227a57188bSDeepika Bhavnani #define PLATFORM_CLUSTER0_CORE_COUNT U(4) 237a57188bSDeepika Bhavnani #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 240bc18309SAnson Huang 251083b2b3SAntonio Nino Diaz #define PWR_DOMAIN_AT_MAX_LVL U(1) 261083b2b3SAntonio Nino Diaz #define PLAT_MAX_PWR_LVL U(2) 271083b2b3SAntonio Nino Diaz #define PLAT_MAX_OFF_STATE U(2) 281083b2b3SAntonio Nino Diaz #define PLAT_MAX_RET_STATE U(1) 290bc18309SAnson Huang 300bc18309SAnson Huang #define BL31_BASE 0x80000000 310bc18309SAnson Huang #define BL31_LIMIT 0x80020000 320bc18309SAnson Huang 330bc18309SAnson Huang #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) 340bc18309SAnson Huang #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) 350bc18309SAnson Huang 360bc18309SAnson Huang #define MAX_XLAT_TABLES 8 370bc18309SAnson Huang #define MAX_MMAP_REGIONS 8 380bc18309SAnson Huang 390bc18309SAnson Huang #define PLAT_GICD_BASE 0x51a00000 400bc18309SAnson Huang #define PLAT_GICR_BASE 0x51b00000 4130617ccaSIgor Opaniuk 4230617ccaSIgor Opaniuk #if defined(IMX_USE_UART0) 430bc18309SAnson Huang #define IMX_BOOT_UART_BASE 0x5a060000 44*8406447fSMarkus Niebel #elif defined(IMX_USE_UART1) 45*8406447fSMarkus Niebel #define IMX_BOOT_UART_BASE 0x5a070000 4630617ccaSIgor Opaniuk #elif defined(IMX_USE_UART3) 4730617ccaSIgor Opaniuk #define IMX_BOOT_UART_BASE 0x5a090000 4830617ccaSIgor Opaniuk #else 4930617ccaSIgor Opaniuk #error "Provide proper UART configuration in IMX_DEBUG_UART" 5030617ccaSIgor Opaniuk #endif 5130617ccaSIgor Opaniuk 520bc18309SAnson Huang #define IMX_BOOT_UART_BAUDRATE 115200 530bc18309SAnson Huang #define IMX_BOOT_UART_CLK_IN_HZ 24000000 540bc18309SAnson Huang #define PLAT_CRASH_UART_BASE IMX_BOOT_UART_BASE 550bc18309SAnson Huang #define PLAT__CRASH_UART_CLK_IN_HZ 24000000 560bc18309SAnson Huang #define IMX_CONSOLE_BAUDRATE 115200 570bc18309SAnson Huang #define SC_IPC_BASE 0x5d1b0000 58e6cf7a46SAnson Huang #define IMX_GPT0_LPCG_BASE 0x5d540000 59e6cf7a46SAnson Huang #define IMX_GPT0_BASE 0x5d140000 60e6cf7a46SAnson Huang #define IMX_WUP_IRQSTR_BASE 0x51090000 61e6cf7a46SAnson Huang #define IMX_REG_BASE 0x50000000 62e6cf7a46SAnson Huang #define IMX_REG_SIZE 0x10000000 630bc18309SAnson Huang 640bc18309SAnson Huang #define COUNTER_FREQUENCY 8000000 650bc18309SAnson Huang 660bc18309SAnson Huang /* non-secure u-boot base */ 670bc18309SAnson Huang #define PLAT_NS_IMAGE_OFFSET 0x80020000 6830617ccaSIgor Opaniuk #define DEBUG_CONSOLE_A35 DEBUG_CONSOLE 690bc18309SAnson Huang 701083b2b3SAntonio Nino Diaz #endif /* PLATFORM_DEF_H */ 71