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Searched refs:MCUCFG_BASE (Results 1 – 25 of 41) sorted by relevance

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/rk3399_ARM-atf/plat/mediatek/drivers/mcusys/v1/
H A Dmcucfg.h16 #define MP2_MISC_CONFIG_BOOT_ADDR_L(cpu) (MCUCFG_BASE + 0x2290 + ((cpu) * 8))
17 #define MP2_MISC_CONFIG_BOOT_ADDR_H(cpu) (MCUCFG_BASE + 0x2294 + ((cpu) * 8))
19 #define MP2_CPUCFG (MCUCFG_BASE + 0x2208)
21 #define MP0_CPUTOP_SPMC_CTL (MCUCFG_BASE + 0x788)
22 #define MP1_CPUTOP_SPMC_CTL (MCUCFG_BASE + 0x78C)
23 #define MP1_CPUTOP_SPMC_SRAM_CTL (MCUCFG_BASE + 0x790)
25 #define CPUSYSx_CPUx_SPMC_CTL(cluster, cpu) (MCUCFG_BASE + 0x1C30 + \
28 #define CPUSYS0_CPU0_SPMC_CTL (MCUCFG_BASE + 0x1C30)
29 #define CPUSYS0_CPU1_SPMC_CTL (MCUCFG_BASE + 0x1C34)
30 #define CPUSYS0_CPU2_SPMC_CTL (MCUCFG_BASE + 0x1C38)
[all …]
/rk3399_ARM-atf/plat/mediatek/include/drivers/mcusys/v1/
H A Dmcucfg.h16 (MCUCFG_BASE + 0x2290 + ((cpu) * 8))
18 (MCUCFG_BASE + 0x2294 + ((cpu) * 8))
20 #define MP2_CPUCFG (MCUCFG_BASE + 0x2208)
25 #define MP0_CPUTOP_SPMC_CTL (MCUCFG_BASE + 0x788)
26 #define MP1_CPUTOP_SPMC_CTL (MCUCFG_BASE + 0x78C)
27 #define MP1_CPUTOP_SPMC_SRAM_CTL (MCUCFG_BASE + 0x790)
51 (MCUCFG_BASE + 0x1C30 + (cluster) * 0x2000 + (cpu) * 4)
53 #define CPUSYS0_CPU0_SPMC_CTL (MCUCFG_BASE + 0x1C30)
54 #define CPUSYS0_CPU1_SPMC_CTL (MCUCFG_BASE + 0x1C34)
55 #define CPUSYS0_CPU2_SPMC_CTL (MCUCFG_BASE + 0x1C38)
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv3_2/
H A Dmt_cpu_pm.h90 #define DREQ20_BIG_VPROC_ISO (MCUCFG_BASE + 0xad8c)
93 #define CORE_RVBRADDR_0_0_L (MCUCFG_BASE + 0xc900)
94 #define CORE_RVBRADDR_0_1_L (MCUCFG_BASE + 0xc908)
95 #define CORE_RVBRADDR_0_2_L (MCUCFG_BASE + 0xc910)
96 #define CORE_RVBRADDR_0_3_L (MCUCFG_BASE + 0xc918)
97 #define CORE_RVBRADDR_0_4_L (MCUCFG_BASE + 0xc920)
98 #define CORE_RVBRADDR_0_5_L (MCUCFG_BASE + 0xc928)
99 #define CORE_RVBRADDR_0_6_L (MCUCFG_BASE + 0xc930)
100 #define CORE_RVBRADDR_0_7_L (MCUCFG_BASE + 0xc938)
101 #define MCUCFG_MP0_CLUSTER_CFG5 (MCUCFG_BASE + 0xc8e4)
H A Dmt_smp.h15 #define CPU_PWR_STATUS (MCUCFG_BASE + 0xA840)
/rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv5_4/
H A Dmt_cpu_pm.h116 #define CORE_RVBRADDR_0_0_L (MCUCFG_BASE + 0x00)
117 #define CORE_RVBRADDR_0_1_L (MCUCFG_BASE + 0x08)
118 #define CORE_RVBRADDR_0_2_L (MCUCFG_BASE + 0x10)
119 #define CORE_RVBRADDR_0_3_L (MCUCFG_BASE + 0x18)
120 #define CORE_RVBRADDR_0_4_L (MCUCFG_BASE + 0x20)
121 #define CORE_RVBRADDR_0_5_L (MCUCFG_BASE + 0x28)
122 #define CORE_RVBRADDR_0_6_L (MCUCFG_BASE + 0x30)
123 #define CORE_RVBRADDR_0_7_L (MCUCFG_BASE + 0x38)
125 #define CORE_RVBRADDR_0_0_H (MCUCFG_BASE + 0x04)
126 #define CORE_RVBRADDR_0_1_H (MCUCFG_BASE + 0x0C)
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8183/drivers/spmc/
H A Dmtspmc_private.h154 #define MCUCFG_CPUSYS0_SPARKVRETCNTRL (MCUCFG_BASE + 0x1c00)
162 #define MCUCFG_CPUSYS0_CPU0_SPMC_CTL (MCUCFG_BASE + 0x1c30)
163 #define MCUCFG_CPUSYS0_CPU1_SPMC_CTL (MCUCFG_BASE + 0x1c34)
164 #define MCUCFG_CPUSYS0_CPU2_SPMC_CTL (MCUCFG_BASE + 0x1c38)
165 #define MCUCFG_CPUSYS0_CPU3_SPMC_CTL (MCUCFG_BASE + 0x1c3c)
171 #define MCUCFG_MP2_BASE (MCUCFG_BASE + 0x2000)
185 #define MCUCFG_MP0_SPMC (MCUCFG_BASE + 0x788)
/rk3399_ARM-atf/plat/mediatek/mt8183/include/
H A Dplatform_def.h25 #define MCUCFG_BASE 0x0c530000 macro
83 #define MT_L2_WRITE_ACCESS_RATE (MCUCFG_BASE + 0x604)
84 #define MP0_CA7L_CACHE_CONFIG (MCUCFG_BASE + 0x7f0)
85 #define MP1_CA7L_CACHE_CONFIG (MCUCFG_BASE + 0x7f4)
86 #define EMI_WFIFO (MCUCFG_BASE + 0x0b5c)
122 #define INT_POL_CTL0 (MCUCFG_BASE + 0xa80)
123 #define SEC_POL_CTL_EN0 (MCUCFG_BASE + 0xa00)
124 #define GIC_SYNC_DCM (MCUCFG_BASE + 0x758)
H A Dmt_gic_v3.h12 #define GIC_INT_MASK (MCUCFG_BASE + 0x5e8)
H A Dplat_dcm.h10 #define MP2_SYNC_DCM (MCUCFG_BASE + 0x2274)
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/dcm/
H A Dmtk_dcm_utils.h16 #define MP_CPUSYS_TOP_BASE (MCUCFG_BASE + 0x8000)
17 #define CPCCFG_REG_BASE (MCUCFG_BASE + 0xA800)
/rk3399_ARM-atf/plat/mediatek/drivers/dcm/
H A Dmtk_dcm_utils.h16 #define MP_CPUSYS_TOP_BASE (MCUCFG_BASE + 0x8000)
17 #define CPCCFG_REG_BASE (MCUCFG_BASE + 0xA800)
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/dcm/
H A Dmtk_dcm_utils.h16 #define MP_CPUSYS_TOP_BASE (MCUCFG_BASE + 0x8000)
17 #define CPCCFG_REG_BASE (MCUCFG_BASE + 0xA800)
/rk3399_ARM-atf/plat/mediatek/include/drivers/mcusys/v3/
H A Dmcucfg.h15 #define MCUSYS_CPC_BASE (MCUCFG_BASE + 0x40000)
66 #define SPMC_CONTROL_CONFIG (MCUCFG_BASE + 0x480)
/rk3399_ARM-atf/plat/mediatek/include/drivers/mcusys/v4/
H A Dmcucfg.h15 #define MCUSYS_CPC_BASE (MCUCFG_BASE + 0x40000)
76 #define SPMC_CONTROL_CONFIG (MCUCFG_BASE + 0x480)
/rk3399_ARM-atf/plat/mediatek/drivers/mcusys/
H A Dmcusys.c12 MAP_REGION_FLAT(MCUCFG_BASE, MCUCFG_REG_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/dfd/
H A Dplat_dfd.h22 #define MCU_BIU_BASE (MCUCFG_BASE)
/rk3399_ARM-atf/plat/mediatek/mt8183/drivers/mcsi/
H A Dmcsi.h86 #define CCI_CLK_CTRL (MCUCFG_BASE + 0x660)
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/dfd/
H A Dplat_dfd.h22 #define MCU_BIU_BASE (MCUCFG_BASE)
/rk3399_ARM-atf/plat/mediatek/include/drivers/mcusys/v2/
H A Dmcucfg.h15 #define MCUSYS_CPC_BASE (MCUCFG_BASE + 0x40000)
/rk3399_ARM-atf/plat/mediatek/drivers/dfd/mt8188/
H A Dplat_dfd.h26 #define MCU_BIU_BASE (MCUCFG_BASE)
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/dfd/
H A Dplat_dfd.h29 #define MCU_BIU_BASE (MCUCFG_BASE)
/rk3399_ARM-atf/plat/mediatek/mt8192/include/
H A Dplatform_def.h15 #define MCUCFG_BASE 0x0c530000 macro
/rk3399_ARM-atf/plat/mediatek/mt8173/include/
H A Dmt8173_def.h26 #define MCUCFG_BASE (IO_PHYS + 0x200000) macro
/rk3399_ARM-atf/plat/mediatek/mt8186/include/
H A Dplatform_def.h14 #define MCUCFG_BASE (0x0C530000) macro
/rk3399_ARM-atf/plat/mediatek/mt8195/include/
H A Dplatform_def.h13 #define MCUCFG_BASE (0x0C530000) macro

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