Lines Matching refs:MCUCFG_BASE
16 #define MP2_MISC_CONFIG_BOOT_ADDR_L(cpu) (MCUCFG_BASE + 0x2290 + ((cpu) * 8))
17 #define MP2_MISC_CONFIG_BOOT_ADDR_H(cpu) (MCUCFG_BASE + 0x2294 + ((cpu) * 8))
19 #define MP2_CPUCFG (MCUCFG_BASE + 0x2208)
21 #define MP0_CPUTOP_SPMC_CTL (MCUCFG_BASE + 0x788)
22 #define MP1_CPUTOP_SPMC_CTL (MCUCFG_BASE + 0x78C)
23 #define MP1_CPUTOP_SPMC_SRAM_CTL (MCUCFG_BASE + 0x790)
25 #define CPUSYSx_CPUx_SPMC_CTL(cluster, cpu) (MCUCFG_BASE + 0x1C30 + \
28 #define CPUSYS0_CPU0_SPMC_CTL (MCUCFG_BASE + 0x1C30)
29 #define CPUSYS0_CPU1_SPMC_CTL (MCUCFG_BASE + 0x1C34)
30 #define CPUSYS0_CPU2_SPMC_CTL (MCUCFG_BASE + 0x1C38)
31 #define CPUSYS0_CPU3_SPMC_CTL (MCUCFG_BASE + 0x1C3C)
33 #define CPUSYS1_CPU0_SPMC_CTL (MCUCFG_BASE + 0x3C30)
34 #define CPUSYS1_CPU1_SPMC_CTL (MCUCFG_BASE + 0x3C34)
35 #define CPUSYS1_CPU2_SPMC_CTL (MCUCFG_BASE + 0x3C38)
36 #define CPUSYS1_CPU3_SPMC_CTL (MCUCFG_BASE + 0x3C3C)
39 #define CPC_MCUSYS_CPC_OFF_THRES (MCUCFG_BASE + 0xA714)
40 #define CPC_MCUSYS_PWR_CTRL (MCUCFG_BASE + 0xA804)
41 #define CPC_MCUSYS_CPC_FLOW_CTRL_CFG (MCUCFG_BASE + 0xA814)
42 #define CPC_MCUSYS_LAST_CORE_REQ (MCUCFG_BASE + 0xA818)
43 #define CPC_MCUSYS_MP_LAST_CORE_RESP (MCUCFG_BASE + 0xA81C)
44 #define CPC_MCUSYS_LAST_CORE_RESP (MCUCFG_BASE + 0xA824)
45 #define CPC_MCUSYS_PWR_ON_MASK (MCUCFG_BASE + 0xA828)
46 #define CPC_SPMC_PWR_STATUS (MCUCFG_BASE + 0xA840)
47 #define CPC_MCUSYS_CPU_ON_SW_HINT_SET (MCUCFG_BASE + 0xA8A8)
48 #define CPC_MCUSYS_CPU_ON_SW_HINT_CLR (MCUCFG_BASE + 0xA8AC)
49 #define CPC_MCUSYS_CPC_DBG_SETTING (MCUCFG_BASE + 0xAB00)
50 #define CPC_MCUSYS_CPC_KERNEL_TIME_L_BASE (MCUCFG_BASE + 0xAB04)
51 #define CPC_MCUSYS_CPC_KERNEL_TIME_H_BASE (MCUCFG_BASE + 0xAB08)
52 #define CPC_MCUSYS_CPC_SYSTEM_TIME_L_BASE (MCUCFG_BASE + 0xAB0C)
53 #define CPC_MCUSYS_CPC_SYSTEM_TIME_H_BASE (MCUCFG_BASE + 0xAB10)
54 #define CPC_MCUSYS_TRACE_SEL (MCUCFG_BASE + 0xAB14)
55 #define CPC_MCUSYS_TRACE_DATA (MCUCFG_BASE + 0xAB20)
56 #define CPC_MCUSYS_CLUSTER_COUNTER (MCUCFG_BASE + 0xAB70)
57 #define CPC_MCUSYS_CLUSTER_COUNTER_CLR (MCUCFG_BASE + 0xAB74)
69 #define SPM_MCUSYS_PWR_CON (MCUCFG_BASE + 0xD200)
70 #define SPM_MP0_CPUTOP_PWR_CON (MCUCFG_BASE + 0xD204)
71 #define SPM_MP0_CPU0_PWR_CON (MCUCFG_BASE + 0xD208)
72 #define SPM_MP0_CPU1_PWR_CON (MCUCFG_BASE + 0xD20C)
73 #define SPM_MP0_CPU2_PWR_CON (MCUCFG_BASE + 0xD210)
74 #define SPM_MP0_CPU3_PWR_CON (MCUCFG_BASE + 0xD214)
75 #define SPM_MP0_CPU4_PWR_CON (MCUCFG_BASE + 0xD218)
76 #define SPM_MP0_CPU5_PWR_CON (MCUCFG_BASE + 0xD21C)
77 #define SPM_MP0_CPU6_PWR_CON (MCUCFG_BASE + 0xD220)
78 #define SPM_MP0_CPU7_PWR_CON (MCUCFG_BASE + 0xD224)
89 #define SPARK2LDO (MCUCFG_BASE + 0x2700)
91 #define MP0_CA7_CACHE_CONFIG (MCUCFG_BASE + 0x000)
92 #define MP0_AXI_CONFIG (MCUCFG_BASE + 0x02C)
93 #define MP0_MISC_CONFIG0 (MCUCFG_BASE + 0x030)
94 #define MP0_MISC_CONFIG1 (MCUCFG_BASE + 0x034)
95 #define MP0_MISC_CONFIG2 (MCUCFG_BASE + 0x038)
96 #define MP0_MISC_CONFIG_BOOT_ADDR(cpu) (MCUCFG_BASE + 0x038 + ((cpu) * 8))
97 #define MP0_MISC_CONFIG3 (MCUCFG_BASE + 0x03C)
98 #define MP0_MISC_CONFIG9 (MCUCFG_BASE + 0x054)
99 #define MP0_CA7_MISC_CONFIG (MCUCFG_BASE + 0x064)
101 #define MP0_RW_RSVD0 (MCUCFG_BASE + 0x06C)
102 #define MP1_CA7_CACHE_CONFIG (MCUCFG_BASE + 0x200)
103 #define MP1_AXI_CONFIG (MCUCFG_BASE + 0x22C)
104 #define MP1_MISC_CONFIG0 (MCUCFG_BASE + 0x230)
105 #define MP1_MISC_CONFIG1 (MCUCFG_BASE + 0x234)
106 #define MP1_MISC_CONFIG2 (MCUCFG_BASE + 0x238)
107 #define MP1_MISC_CONFIG_BOOT_ADDR(cpu) (MCUCFG_BASE + 0x238 + ((cpu) * 8))
108 #define MP1_MISC_CONFIG3 (MCUCFG_BASE + 0x23C)
109 #define MP1_MISC_CONFIG9 (MCUCFG_BASE + 0x254)
110 #define MP1_CA7_MISC_CONFIG (MCUCFG_BASE + 0x264)
112 #define CCI_ADB400_DCM_CONFIG (MCUCFG_BASE + 0x740)
113 #define SYNC_DCM_CONFIG (MCUCFG_BASE + 0x744)
115 #define MP0_CLUSTER_CFG0 (MCUCFG_BASE + 0xC8D0)
117 #define MP0_SPMC (MCUCFG_BASE + 0x788)
118 #define MP1_SPMC (MCUCFG_BASE + 0x78C)
119 #define MP2_AXI_CONFIG (MCUCFG_BASE + 0x220C)
138 #define CPUSYS0_SPARKVRETCNTRL (MCUCFG_BASE+0x1c00)
139 #define CPUSYS0_SPARKEN (MCUCFG_BASE+0x1c04)
140 #define CPUSYS0_AMUXSEL (MCUCFG_BASE+0x1c08)
141 #define CPUSYS1_SPARKVRETCNTRL (MCUCFG_BASE+0x3c00)
142 #define CPUSYS1_SPARKEN (MCUCFG_BASE+0x3c04)
143 #define CPUSYS1_AMUXSEL (MCUCFG_BASE+0x3c08)
145 #define MP2_PWR_RST_CTL (MCUCFG_BASE + 0x2008)
146 #define MP2_PTP3_CPUTOP_SPMC0 (MCUCFG_BASE + 0x22A0)
147 #define MP2_PTP3_CPUTOP_SPMC1 (MCUCFG_BASE + 0x22A4)
149 #define MP2_COQ (MCUCFG_BASE + 0x22BC)
152 #define MP2_CA15M_MON_SEL (MCUCFG_BASE + 0x2400)
153 #define MP2_CA15M_MON_L (MCUCFG_BASE + 0x2404)
155 #define CPUSYS2_CPU0_SPMC_CTL (MCUCFG_BASE + 0x2430)
156 #define CPUSYS2_CPU1_SPMC_CTL (MCUCFG_BASE + 0x2438)
157 #define CPUSYS2_CPU0_SPMC_STA (MCUCFG_BASE + 0x2434)
158 #define CPUSYS2_CPU1_SPMC_STA (MCUCFG_BASE + 0x243C)
160 #define MP0_CA7L_DBG_PWR_CTRL (MCUCFG_BASE + 0x068)
161 #define MP1_CA7L_DBG_PWR_CTRL (MCUCFG_BASE + 0x268)
162 #define BIG_DBG_PWR_CTRL (MCUCFG_BASE + 0x75C)