1*95e974faSKai Liang /* 2*95e974faSKai Liang * Copyright (c) 2025, MediaTek Inc. All rights reserved. 3*95e974faSKai Liang * 4*95e974faSKai Liang * SPDX-License-Identifier: BSD-3-Clause 5*95e974faSKai Liang */ 6*95e974faSKai Liang 7*95e974faSKai Liang #ifndef MCUCFG_H 8*95e974faSKai Liang #define MCUCFG_H 9*95e974faSKai Liang 10*95e974faSKai Liang #ifndef __ASSEMBLER__ 11*95e974faSKai Liang #include <stdint.h> 12*95e974faSKai Liang #endif /*__ASSEMBLER__*/ 13*95e974faSKai Liang #include <platform_def.h> 14*95e974faSKai Liang 15*95e974faSKai Liang #define MCUSYS_CPC_BASE (MCUCFG_BASE + 0x40000) 16*95e974faSKai Liang 17*95e974faSKai Liang /* CPC related registers */ 18*95e974faSKai Liang #define CPC_FCM_SPMC_SW_CFG2 (MCUSYS_CPC_BASE + 0x004) 19*95e974faSKai Liang #define CPC_FCM_SPMC_PWR_STATUS (MCUSYS_CPC_BASE + 0x010) 20*95e974faSKai Liang #define CPC_MCUSYS_CPC_OFF_THRES (MCUSYS_CPC_BASE + 0x014) 21*95e974faSKai Liang #define CPC_MCUSYS_PWR_CTRL (MCUSYS_CPC_BASE + 0x104) 22*95e974faSKai Liang #define CPC_MCUSYS_CPC_FLOW_CTRL_CFG (MCUSYS_CPC_BASE + 0x114) 23*95e974faSKai Liang #define CPC_MCUSYS_LAST_CORE_REQ (MCUSYS_CPC_BASE + 0x118) 24*95e974faSKai Liang #define CPC_MCUSYS_MP_LAST_CORE_RESP (MCUSYS_CPC_BASE + 0x11c) 25*95e974faSKai Liang #define CPC_MCUSYS_LAST_CORE_RESP (MCUSYS_CPC_BASE + 0x124) 26*95e974faSKai Liang #define CPC_MCUSYS_PWR_ON_MASK (MCUSYS_CPC_BASE + 0x128) 27*95e974faSKai Liang #define CPC_SPMC_PWR_STATUS (MCUSYS_CPC_BASE + 0x140) 28*95e974faSKai Liang #define CPC_CORE_CUR_FSM (MCUSYS_CPC_BASE + 0x144) 29*95e974faSKai Liang #define CPC_WAKEUP_REQ (MCUSYS_CPC_BASE + 0x14c) 30*95e974faSKai Liang #define CPC_MCUSYS_CPU_ON_SW_HINT_SET (MCUSYS_CPC_BASE + 0x1a8) 31*95e974faSKai Liang #define CPC_MCUSYS_CPU_ON_SW_HINT_CLR (MCUSYS_CPC_BASE + 0x1ac) 32*95e974faSKai Liang #define CPC_MCUSYS_CPC_DBG_SETTING (MCUSYS_CPC_BASE + 0x200) 33*95e974faSKai Liang #define CPC_MCUSYS_CPC_KERNEL_TIME_L_BASE (MCUSYS_CPC_BASE + 0x204) 34*95e974faSKai Liang #define CPC_MCUSYS_CPC_KERNEL_TIME_H_BASE (MCUSYS_CPC_BASE + 0x208) 35*95e974faSKai Liang #define CPC_MCUSYS_CPC_SYSTEM_TIME_L_BASE (MCUSYS_CPC_BASE + 0x20c) 36*95e974faSKai Liang #define CPC_MCUSYS_CPC_SYSTEM_TIME_H_BASE (MCUSYS_CPC_BASE + 0x210) 37*95e974faSKai Liang #define CPC_MCUSYS_TRACE_SEL (MCUSYS_CPC_BASE + 0x214) 38*95e974faSKai Liang #define CPC_MCUSYS_TRACE_DATA (MCUSYS_CPC_BASE + 0x220) 39*95e974faSKai Liang #define CPC_CPU0_LATENCY (MCUSYS_CPC_BASE + 0x240) 40*95e974faSKai Liang #define CPC_CLUSTER_OFF_LATENCY (MCUSYS_CPC_BASE + 0x260) 41*95e974faSKai Liang #define CPC_CLUSTER_ON_LATENCY (MCUSYS_CPC_BASE + 0x264) 42*95e974faSKai Liang #define CPC_MCUSYS_LATENCY (MCUSYS_CPC_BASE + 0x268) 43*95e974faSKai Liang #define CPC_MCUSYS_CLUSTER_COUNTER (MCUSYS_CPC_BASE + 0x270) 44*95e974faSKai Liang #define CPC_MCUSYS_CLUSTER_COUNTER_CLR (MCUSYS_CPC_BASE + 0x274) 45*95e974faSKai Liang #define CPC_CPU_LATENCY(cpu) (CPC_CPU0_LATENCY + 4 * (cpu)) 46*95e974faSKai Liang 47*95e974faSKai Liang #define CPC_WDT_LATCH_INFO1 (MCUSYS_CPC_BASE + 0x280) 48*95e974faSKai Liang #define CPC_WDT_LATCH_INFO2 (MCUSYS_CPC_BASE + 0x284) 49*95e974faSKai Liang #define CPC_WDT_LATCH_INFO3 (MCUSYS_CPC_BASE + 0x288) 50*95e974faSKai Liang #define CPC_WDT_LATCH_INFO4 (MCUSYS_CPC_BASE + 0x28c) 51*95e974faSKai Liang #define CPC_WDT_LATCH_INFO5 (MCUSYS_CPC_BASE + 0x290) 52*95e974faSKai Liang 53*95e974faSKai Liang /* CPC_MCUSYS_CPC_FLOW_CTRL_CFG bit control */ 54*95e974faSKai Liang #define CPC_CTRL_ENABLE BIT(16) 55*95e974faSKai Liang #define SSPM_ALL_PWR_CTRL_EN BIT(13) /* for cpu-hotplug */ 56*95e974faSKai Liang #define GIC_WAKEUP_IGNORE(cpu) BIT(21 + (cpu)) 57*95e974faSKai Liang 58*95e974faSKai Liang #define CPC_MCUSYS_CPC_RESET_ON_KEEP_ON BIT(17) 59*95e974faSKai Liang #define CPC_MCUSYS_CPC_RESET_PWR_ON_EN BIT(20) 60*95e974faSKai Liang 61*95e974faSKai Liang #define CPC_CORE_FSM_ON BIT(3) 62*95e974faSKai Liang 63*95e974faSKai Liang #define CPC_WAKEUP_STAT_NONE 0x0 64*95e974faSKai Liang 65*95e974faSKai Liang #endif /* __MCUCFG_H__ */ 66