Lines Matching refs:MCUCFG_BASE
16 (MCUCFG_BASE + 0x2290 + ((cpu) * 8))
18 (MCUCFG_BASE + 0x2294 + ((cpu) * 8))
20 #define MP2_CPUCFG (MCUCFG_BASE + 0x2208)
25 #define MP0_CPUTOP_SPMC_CTL (MCUCFG_BASE + 0x788)
26 #define MP1_CPUTOP_SPMC_CTL (MCUCFG_BASE + 0x78C)
27 #define MP1_CPUTOP_SPMC_SRAM_CTL (MCUCFG_BASE + 0x790)
51 (MCUCFG_BASE + 0x1C30 + (cluster) * 0x2000 + (cpu) * 4)
53 #define CPUSYS0_CPU0_SPMC_CTL (MCUCFG_BASE + 0x1C30)
54 #define CPUSYS0_CPU1_SPMC_CTL (MCUCFG_BASE + 0x1C34)
55 #define CPUSYS0_CPU2_SPMC_CTL (MCUCFG_BASE + 0x1C38)
56 #define CPUSYS0_CPU3_SPMC_CTL (MCUCFG_BASE + 0x1C3C)
58 #define CPUSYS1_CPU0_SPMC_CTL (MCUCFG_BASE + 0x3C30)
59 #define CPUSYS1_CPU1_SPMC_CTL (MCUCFG_BASE + 0x3C34)
60 #define CPUSYS1_CPU2_SPMC_CTL (MCUCFG_BASE + 0x3C38)
61 #define CPUSYS1_CPU3_SPMC_CTL (MCUCFG_BASE + 0x3C3C)
84 #define CPC_MCUSYS_CPC_OFF_THRES (MCUCFG_BASE + 0xa714)
85 #define CPC_MCUSYS_PWR_CTRL (MCUCFG_BASE + 0xa804)
86 #define CPC_MCUSYS_CPC_FLOW_CTRL_CFG (MCUCFG_BASE + 0xa814)
87 #define CPC_MCUSYS_LAST_CORE_REQ (MCUCFG_BASE + 0xa818)
88 #define CPC_MCUSYS_MP_LAST_CORE_RESP (MCUCFG_BASE + 0xa81c)
89 #define CPC_MCUSYS_LAST_CORE_RESP (MCUCFG_BASE + 0xa824)
90 #define CPC_MCUSYS_PWR_ON_MASK (MCUCFG_BASE + 0xa828)
91 #define CPC_SPMC_PWR_STATUS (MCUCFG_BASE + 0xa840)
92 #define CPC_WAKEUP_REQ (MCUCFG_BASE + 0xa84c)
93 #define CPC_MCUSYS_CPU_ON_SW_HINT_SET (MCUCFG_BASE + 0xa8a8)
94 #define CPC_MCUSYS_CPU_ON_SW_HINT_CLR (MCUCFG_BASE + 0xa8ac)
95 #define CPC_MCUSYS_CPC_DBG_SETTING (MCUCFG_BASE + 0xab00)
96 #define CPC_MCUSYS_CPC_KERNEL_TIME_L_BASE (MCUCFG_BASE + 0xab04)
97 #define CPC_MCUSYS_CPC_KERNEL_TIME_H_BASE (MCUCFG_BASE + 0xab08)
98 #define CPC_MCUSYS_CPC_SYSTEM_TIME_L_BASE (MCUCFG_BASE + 0xab0c)
99 #define CPC_MCUSYS_CPC_SYSTEM_TIME_H_BASE (MCUCFG_BASE + 0xab10)
100 #define CPC_MCUSYS_TRACE_SEL (MCUCFG_BASE + 0xab14)
101 #define CPC_MCUSYS_TRACE_DATA (MCUCFG_BASE + 0xab20)
102 #define CPC_CPU0_LATENCY (MCUCFG_BASE + 0xab40)
103 #define CPC_CLUSTER_OFF_LATENCY (MCUCFG_BASE + 0xab60)
104 #define CPC_CLUSTER_ON_LATENCY (MCUCFG_BASE + 0xab64)
105 #define CPC_MCUSYS_LATENCY (MCUCFG_BASE + 0xab68)
106 #define CPC_MCUSYS_CLUSTER_COUNTER (MCUCFG_BASE + 0xab70)
107 #define CPC_MCUSYS_CLUSTER_COUNTER_CLR (MCUCFG_BASE + 0xab74)
123 #define SPM_MCUSYS_PWR_CON (MCUCFG_BASE + 0xd200)
124 #define SPM_MP0_CPUTOP_PWR_CON (MCUCFG_BASE + 0xd204)
125 #define SPM_MP0_CPU0_PWR_CON (MCUCFG_BASE + 0xd208)
126 #define SPM_MP0_CPU1_PWR_CON (MCUCFG_BASE + 0xd20c)
127 #define SPM_MP0_CPU2_PWR_CON (MCUCFG_BASE + 0xd210)
128 #define SPM_MP0_CPU3_PWR_CON (MCUCFG_BASE + 0xd214)
129 #define SPM_MP0_CPU4_PWR_CON (MCUCFG_BASE + 0xd218)
130 #define SPM_MP0_CPU5_PWR_CON (MCUCFG_BASE + 0xd21c)
131 #define SPM_MP0_CPU6_PWR_CON (MCUCFG_BASE + 0xd220)
132 #define SPM_MP0_CPU7_PWR_CON (MCUCFG_BASE + 0xd224)
134 #define MCSIC_DCM0 (MCUCFG_BASE + 0xa440)
135 #define MCSIC_DCM1 (MCUCFG_BASE + 0xa444)
146 #define SPARK2LDO (MCUCFG_BASE + 0x2700)
148 #define MP0_CA7_CACHE_CONFIG (MCUCFG_BASE + 0x000)
149 #define MP0_AXI_CONFIG (MCUCFG_BASE + 0x02C)
150 #define MP0_MISC_CONFIG0 (MCUCFG_BASE + 0x030)
151 #define MP0_MISC_CONFIG1 (MCUCFG_BASE + 0x034)
152 #define MP0_MISC_CONFIG2 (MCUCFG_BASE + 0x038)
153 #define MP0_MISC_CONFIG_BOOT_ADDR(cpu) (MCUCFG_BASE + 0x038 + (cpu) * 8)
154 #define MP0_MISC_CONFIG3 (MCUCFG_BASE + 0x03C)
155 #define MP0_MISC_CONFIG9 (MCUCFG_BASE + 0x054)
156 #define MP0_CA7_MISC_CONFIG (MCUCFG_BASE + 0x064)
158 #define MP0_RW_RSVD0 (MCUCFG_BASE + 0x06C)
160 #define MP1_CA7_CACHE_CONFIG (MCUCFG_BASE + 0x200)
161 #define MP1_AXI_CONFIG (MCUCFG_BASE + 0x22C)
162 #define MP1_MISC_CONFIG0 (MCUCFG_BASE + 0x230)
163 #define MP1_MISC_CONFIG1 (MCUCFG_BASE + 0x234)
164 #define MP1_MISC_CONFIG2 (MCUCFG_BASE + 0x238)
165 #define MP1_MISC_CONFIG_BOOT_ADDR(cpu) (MCUCFG_BASE + 0x238 + ((cpu) * 8))
166 #define MP1_MISC_CONFIG3 (MCUCFG_BASE + 0x23C)
167 #define MP1_MISC_CONFIG9 (MCUCFG_BASE + 0x254)
168 #define MP1_CA7_MISC_CONFIG (MCUCFG_BASE + 0x264)
170 #define CCI_ADB400_DCM_CONFIG (MCUCFG_BASE + 0x740)
171 #define SYNC_DCM_CONFIG (MCUCFG_BASE + 0x744)
173 #define MP0_CLUSTER_CFG0 (MCUCFG_BASE + 0xC8D0)
175 #define MP0_SPMC (MCUCFG_BASE + 0x788)
176 #define MP1_SPMC (MCUCFG_BASE + 0x78C)
177 #define MP2_AXI_CONFIG (MCUCFG_BASE + 0x220C)
196 #define CPUSYS0_SPARKVRETCNTRL (MCUCFG_BASE + 0x1c00)
197 #define CPUSYS0_SPARKEN (MCUCFG_BASE + 0x1c04)
198 #define CPUSYS0_AMUXSEL (MCUCFG_BASE + 0x1c08)
199 #define CPUSYS1_SPARKVRETCNTRL (MCUCFG_BASE + 0x3c00)
200 #define CPUSYS1_SPARKEN (MCUCFG_BASE + 0x3c04)
201 #define CPUSYS1_AMUXSEL (MCUCFG_BASE + 0x3c08)
203 #define MP2_PWR_RST_CTL (MCUCFG_BASE + 0x2008)
204 #define MP2_PTP3_CPUTOP_SPMC0 (MCUCFG_BASE + 0x22A0)
205 #define MP2_PTP3_CPUTOP_SPMC1 (MCUCFG_BASE + 0x22A4)
207 #define MP2_COQ (MCUCFG_BASE + 0x22BC)
210 #define MP2_CA15M_MON_SEL (MCUCFG_BASE + 0x2400)
211 #define MP2_CA15M_MON_L (MCUCFG_BASE + 0x2404)
213 #define CPUSYS2_CPU0_SPMC_CTL (MCUCFG_BASE + 0x2430)
214 #define CPUSYS2_CPU1_SPMC_CTL (MCUCFG_BASE + 0x2438)
215 #define CPUSYS2_CPU0_SPMC_STA (MCUCFG_BASE + 0x2434)
216 #define CPUSYS2_CPU1_SPMC_STA (MCUCFG_BASE + 0x243C)
218 #define MP0_CA7L_DBG_PWR_CTRL (MCUCFG_BASE + 0x068)
219 #define MP1_CA7L_DBG_PWR_CTRL (MCUCFG_BASE + 0x268)
220 #define BIG_DBG_PWR_CTRL (MCUCFG_BASE + 0x75C)