1*49d3bd8cSGarmin Chang /* 2*49d3bd8cSGarmin Chang * Copyright (c) 2021, MediaTek Inc. All rights reserved. 3*49d3bd8cSGarmin Chang * 4*49d3bd8cSGarmin Chang * SPDX-License-Identifier: BSD-3-Clause 5*49d3bd8cSGarmin Chang */ 6*49d3bd8cSGarmin Chang 7*49d3bd8cSGarmin Chang #ifndef MTK_DCM_UTILS_H 8*49d3bd8cSGarmin Chang #define MTK_DCM_UTILS_H 9*49d3bd8cSGarmin Chang 10*49d3bd8cSGarmin Chang #include <stdbool.h> 11*49d3bd8cSGarmin Chang 12*49d3bd8cSGarmin Chang #include <mtk_dcm.h> 13*49d3bd8cSGarmin Chang #include <platform_def.h> 14*49d3bd8cSGarmin Chang 15*49d3bd8cSGarmin Chang /* Base */ 16*49d3bd8cSGarmin Chang #define MP_CPUSYS_TOP_BASE (MCUCFG_BASE + 0x8000) 17*49d3bd8cSGarmin Chang #define CPCCFG_REG_BASE (MCUCFG_BASE + 0xA800) 18*49d3bd8cSGarmin Chang 19*49d3bd8cSGarmin Chang /* Register Definition */ 20*49d3bd8cSGarmin Chang #define MP_CPUSYS_TOP_CPU_PLLDIV_CFG0 (MP_CPUSYS_TOP_BASE + 0x22a0) 21*49d3bd8cSGarmin Chang #define MP_CPUSYS_TOP_CPU_PLLDIV_CFG1 (MP_CPUSYS_TOP_BASE + 0x22a4) 22*49d3bd8cSGarmin Chang #define MP_CPUSYS_TOP_BUS_PLLDIV_CFG (MP_CPUSYS_TOP_BASE + 0x22e0) 23*49d3bd8cSGarmin Chang #define MP_CPUSYS_TOP_MCSIC_DCM0 (MP_CPUSYS_TOP_BASE + 0x2440) 24*49d3bd8cSGarmin Chang #define MP_CPUSYS_TOP_MP_ADB_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x2500) 25*49d3bd8cSGarmin Chang #define MP_CPUSYS_TOP_MP_ADB_DCM_CFG4 (MP_CPUSYS_TOP_BASE + 0x2510) 26*49d3bd8cSGarmin Chang #define MP_CPUSYS_TOP_MP_MISC_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x2518) 27*49d3bd8cSGarmin Chang #define MP_CPUSYS_TOP_MCUSYS_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x25c0) 28*49d3bd8cSGarmin Chang #define CPCCFG_REG_EMI_WFIFO (CPCCFG_REG_BASE + 0x100) 29*49d3bd8cSGarmin Chang #define MP_CPUSYS_TOP_MP0_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x4880) 30*49d3bd8cSGarmin Chang #define MP_CPUSYS_TOP_MP0_DCM_CFG7 (MP_CPUSYS_TOP_BASE + 0x489c) 31*49d3bd8cSGarmin Chang 32*49d3bd8cSGarmin Chang /* MP_CPUSYS_TOP */ 33*49d3bd8cSGarmin Chang bool dcm_mp_cpusys_top_adb_dcm_is_on(void); 34*49d3bd8cSGarmin Chang void dcm_mp_cpusys_top_adb_dcm(bool on); 35*49d3bd8cSGarmin Chang bool dcm_mp_cpusys_top_apb_dcm_is_on(void); 36*49d3bd8cSGarmin Chang void dcm_mp_cpusys_top_apb_dcm(bool on); 37*49d3bd8cSGarmin Chang bool dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(void); 38*49d3bd8cSGarmin Chang void dcm_mp_cpusys_top_bus_pll_div_dcm(bool on); 39*49d3bd8cSGarmin Chang bool dcm_mp_cpusys_top_core_stall_dcm_is_on(void); 40*49d3bd8cSGarmin Chang void dcm_mp_cpusys_top_core_stall_dcm(bool on); 41*49d3bd8cSGarmin Chang bool dcm_mp_cpusys_top_cpubiu_dcm_is_on(void); 42*49d3bd8cSGarmin Chang void dcm_mp_cpusys_top_cpubiu_dcm(bool on); 43*49d3bd8cSGarmin Chang bool dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(void); 44*49d3bd8cSGarmin Chang void dcm_mp_cpusys_top_cpu_pll_div_0_dcm(bool on); 45*49d3bd8cSGarmin Chang bool dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(void); 46*49d3bd8cSGarmin Chang void dcm_mp_cpusys_top_cpu_pll_div_1_dcm(bool on); 47*49d3bd8cSGarmin Chang bool dcm_mp_cpusys_top_fcm_stall_dcm_is_on(void); 48*49d3bd8cSGarmin Chang void dcm_mp_cpusys_top_fcm_stall_dcm(bool on); 49*49d3bd8cSGarmin Chang bool dcm_mp_cpusys_top_last_cor_idle_dcm_is_on(void); 50*49d3bd8cSGarmin Chang void dcm_mp_cpusys_top_last_cor_idle_dcm(bool on); 51*49d3bd8cSGarmin Chang bool dcm_mp_cpusys_top_misc_dcm_is_on(void); 52*49d3bd8cSGarmin Chang void dcm_mp_cpusys_top_misc_dcm(bool on); 53*49d3bd8cSGarmin Chang bool dcm_mp_cpusys_top_mp0_qdcm_is_on(void); 54*49d3bd8cSGarmin Chang void dcm_mp_cpusys_top_mp0_qdcm(bool on); 55*49d3bd8cSGarmin Chang /* CPCCFG_REG */ 56*49d3bd8cSGarmin Chang bool dcm_cpccfg_reg_emi_wfifo_is_on(void); 57*49d3bd8cSGarmin Chang void dcm_cpccfg_reg_emi_wfifo(bool on); 58*49d3bd8cSGarmin Chang 59*49d3bd8cSGarmin Chang #endif 60