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/rk3399_ARM-atf/fdts/
H A Dfvp-defs-dynamiq.dtsi27 * n - CPU number
30 #define CPU(n, r) \ macro
31 CPU##n:cpu@r## { \
43 cpu = <&CONC(CPU, __COUNTER__)>; \
55 cpu = <&CPU##n>;\
62 CPU(0, 0)
65 CPU(0, 0) \
66 CPU(1, 1)
76 CPU(0, 0) \
77 CPU(1, 100)
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H A Drdaspen-defs.dtsi12 #define CPU(cluster_num, cluster_core_num, cpu_num, mpid) \ macro
13 CPU##cpu_num:cpu@mpid## { \
41 cpu = <&CPU##cpu_num>; \
72 CPU(0, 0, 0, 0)
79 CPU(0, 0, 0, 0) \
80 CPU(0, 1, 1, 100)
88 CPU(0, 0, 0, 0) \
89 CPU(0, 1, 1, 100) \
90 CPU(0, 2, 2, 200)
99 CPU(0, 0, 0, 0) \
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H A Dfvp-defs.dtsi33 /* CPU's cluster */
36 /* CPU's position in cluster */
40 CPU##n:cpu@CONC(c, CONC(p, AFF)) {
59 * n - CPU number
61 #define CPU(n, c, p) \ macro
77 #define CPU_1 CPU(1, c1, p1) /* CPU1: 0.1; 1.0 */
92 #define CPU_2 CPU(2, c2, p2) /* CPU2: 0.2; 1.0; 2.0 */
112 #define CPU_3 CPU(3, c3, p3) /* CPU3: 0.3; 1.0; 1.1; 3.0 */
140 #define CPU_4 CPU(4, c4, p4) /* CPU4: 1.0; 1.1; 2.0 */
141 #define CPU_5 CPU(5, c5, p5) /* CPU5: 1.1; 1.2; 2.1 */
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H A Drdv3-defs.dtsi14 CPU##n:cpu@n##0000 {
29 * n - CPU number
31 #define CPU(n) \ macro
/rk3399_ARM-atf/plat/arm/board/neoverse_rd/platform/rdv3/fdts/
H A Drdv3_spmc_sp_manifest.dts49 CPU(F)
50 CPU(E)
51 CPU(D)
52 CPU(C)
53 CPU(B)
54 CPU(A)
55 CPU(9)
56 CPU(8)
58 CPU(7)
59 CPU(6)
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/rk3399_ARM-atf/docs/design/
H A Dcpu-specific-build-macros.rst1 Arm CPU Specific Build Macros
4 This document describes the various build options present in the CPU specific
6 for a specific CPU on a platform.
29 platform contains at least 1 CPU that requires dynamic mitigation.
34 least 1 CPU that requires this mitigation. Defaults to 1.
39 at least 1 CPU that requires this mitigation. Defaults to 1.
43 least 1 CPU that requires this mitigation. Defaults to 1.
47 CPU Errata Workarounds
51 are applied to each CPU by the reset handler. The errata details can be found
52 in the CPU specifi
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H A Dreset-design.rst1 CPU Reset
4 This document describes the high-level design of the framework to handle CPU
32 Programmable CPU reset address
35 By default, TF-A assumes that the CPU reset address is not programmable.
41 ``RVBAR_EL3``) is programmable then it is possible to make each CPU start directly
54 Cold boot on a single CPU
63 If the platform guarantees that only a single CPU will ever be brought up then
64 no arbitration is required. The notion of primary/secondary CPU itself no longer
67 |Reset code flow with single CPU released out of reset|
77 Programmable CPU reset address, Cold boot on a single CPU
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H A Dfirmware-design.rst14 (for example, secondary CPU boot, hotplug and idle). Normal world software can
40 primary CPU, and the remaining CPUs are considered secondary CPUs. The primary
41 CPU is chosen through platform-specific means. The cold boot path is mainly
42 executed by the primary CPU, other than essential CPU initialization executed by
44 the primary CPU has performed enough initialization to boot them.
46 Refer to the :ref:`CPU Reset` for more information on the effect of the
159 Whenever a CPU is released from reset, BL1 needs to distinguish between a warm
162 of a warm boot, a CPU is expected to continue execution from a separate
165 the :ref:`Porting Guide`) while the primary CPU executes the remaining cold boot
169 :ref:`CPU Reset` for more information on the effect of the
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/rk3399_ARM-atf/docs/components/
H A Dnuma-per-cpu.rst1 NUMA-Aware Per-CPU Framework
15 CPUs on remote nodes. In TF-A's current implementation, per-CPU data (for
22 node may be insufficient to hold per-CPU data for all CPUs. This constraint
38 traversal. When per-CPU data is centralized on a single node, CPUs on remote
44 To address these challenges, TF-A provides the NUMA-Aware Per-CPU Framework. The
45 framework optimizes the allocation and access of per-CPU objects by letting
52 **allocating**, **defining**, and **accessing** per-CPU data in a NUMA-aware
60 to **allocate** per-CPU global variables and ensure that these objects reside in
61 the local memory of each NUMA node. The figure below illustrates how per-CPU
71 \`.bss\` and \`xlat\` to represent per-CPU data allocation, while
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H A Dcontext-management-library.rst20 with a context management library to handle the context of the CPU, managing the
27 to preserve the state of the CPU at the next lower exception level (EL) in a given
32 In a trusted system at any instance, a given CPU could be executing in one of the
37 If the CPU switches across security states (for example: from Non-secure to Secure
47 that are not influenced by Normal World operations. Therefore, for each CPU, we
49 world do not leak or impact the execution of the CPU in other worlds.
58 This includes implementing CPU context initialization and management routines,
60 firmware, which are collectively referred to as CPU Context Management.
176 #. ``cpu_data.h`` : contains the public interface to Per CPU data structure.
202 CPU Data Structure
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H A Darm-sip-service.rst39 AArch32, or from AArch32 to AArch64, for the calling CPU. This service is only
66 switched, the parameters *Cookie hi* and *Cookie lo* are passed in CPU registers
69 This call can only be made on the primary CPU, before any secondaries were
73 entered for the first time, following power on. This means CPU registers that
76 CPU endianness, however, is preserved from the previous execution state. Note
77 that this switches the execution state of the calling CPU only. This is not a
88 Instead, execution starts at the supplied entry point, with the CPU registers 0
/rk3399_ARM-atf/docs/perf/
H A Dpsci-performance-juno.rst25 Juno supports CPU, cluster and system power down states, corresponding to power
292 CPUs 4-5 refer to CPUs in the big cluster (A57). In all cases CPU 4 is the lead
293 CPU.
302 | CPU | ``PSCI_ENTRY`` (us) | ``PSCI_EXIT`` (us) | ``CFLUSH_OVERHEAD`` (us) |
318 observed due to TF PSCI lock contention. In the worst case, CPU 3 has to wait
326 The ``CFLUSH_OVERHEAD`` time for CPU 5 is a lot larger than that for CPU 3
334 | CPU | ``PSCI_ENTRY`` (us) | ``PSCI_EXIT`` (us) | ``CFLUSH_OVERHEAD`` (us) |
353 AP CPU to enter WFI before making the channel available to other CPUs, which
356 On platforms with a more efficient CPU power down mechanism, it should be
369 | CPU | ``PSCI_ENTRY`` (us) | ``PSCI_EXIT`` (us) | ``CFLUSH_OVERHEAD`` (us) |
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H A Dpsci-performance-methodology.rst21 brings them and the lead CPU to a common synchronization point. The lead CPU
24 - **Sequential Tests** This type of test powers on each non-lead CPU in
25 sequence. The lead CPU initiates the test on a non-lead CPU then waits for the
26 test to complete before proceeding to the next non-lead CPU. The lead CPU then
30 the values for each CPU are sometimes interchanged, depending on the order in
/rk3399_ARM-atf/include/lib/per_cpu/
H A Dper_cpu.h38 #define PER_CPU_BY_INDEX(NAME, CPU) \ argument
40 (per_cpu_by_index_compute((CPU), (const void *)&(NAME))))
/rk3399_ARM-atf/docs/plat/qti/
H A Dmsm8916.rst6 | System-on-Chip (SoC) | TF-A Platform | Application CPU | Supports |
48 secondary CPU cores (PSCI ``CPU_ON``) is supported. Basic CPU core power
162 INFO: BL31: cortex_a53: CPU workaround for 819472 was applied
163 INFO: BL31: cortex_a53: CPU workaround for 824069 was applied
164 INFO: BL31: cortex_a53: CPU workaround for 826319 was applied
165 INFO: BL31: cortex_a53: CPU workaround for 827319 was applied
166 INFO: BL31: cortex_a53: CPU workaround for 835769 was applied
167 INFO: BL31: cortex_a53: CPU workaround for disable_non_temporal_hint was applied
168 INFO: BL31: cortex_a53: CPU workaround for 843419 was applied
169 INFO: BL31: cortex_a53: CPU workaround for 1530924 was applied
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/rk3399_ARM-atf/docs/security_advisories/
H A Dsecurity-advisory-tfv-8.rst26 When taking an exception to EL3, BL31 saves the CPU context. The aim is to
29 ``x0`` to ``x3`` are not part of the CPU context saved on the stack.
33 into the CPU context, typically using one of the ``SMC_RETx()`` macros provided
38 CPU context stored on the stack. This includes registers ``x0`` to ``x3``, as
46 * CPU context. x30 register must be explicitly restored by the caller.
53 remaining ones are left unchanged in the CPU context. As a result,
67 For this reason, TF-A does not save ``x0`` to ``x3`` in the CPU context on an
H A Dsecurity-advisory-tfv-6.rst113 effective at invalidating the branch predictor on Cortex-A15. For that CPU, set
123 Refer to `Arm CPU Security Bulletin-Spectre/Meltdown`_ for list of impacted CPUs.
125 For more information about non-Arm CPUs, please contact the CPU vendor.
137 Refer to `Arm CPU Security Bulletin-Spectre/Meltdown`_ for list of impacted CPUs.
164 .. _Arm CPU Security Bulletin-Spectre/Meltdown: https://developer.arm.com/documentation/110280/late…
H A Dsecurity-advisory-tfv-9.rst46 level for the given CPU. This is done as early as possible on entry into EL3,
103 this vulnerability for Cortex-A72 CPU versions that support the CSV2 feature
116 For more information about non-Arm CPUs, please contact the CPU vendor.
H A Dsecurity-advisory-tfv-7.rst45 For each affected CPU type, TF-A implements one of the two following mitigation
47 have a system performance impact, which varies for each CPU type and use-case.
98 TF-A implements this approach for the following affected CPU:
/rk3399_ARM-atf/docs/plat/arm/fvp/
H A Dfvp-build-options.rst22 - ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU
46 inactive/fused CPU cores as read-only. The default value of this option
47 is ``0``, which means the redistributor pages of all CPU cores are marked
/rk3399_ARM-atf/docs/
H A Dporting-guide.rst99 used to allocate any data structures that are accessed both when a CPU is
131 Defines the normal stack memory available to each CPU. This constant is used
689 For each CPU, the reset vector code is responsible for the following tasks:
693 #. In the case of a cold boot and the CPU being a secondary CPU, ensuring that
694 the CPU is placed in a platform-specific state until the primary CPU
697 #. In the case of a warm boot, ensuring that the CPU jumps to a platform-
714 distinguishing between a warm and cold reset for the current CPU using
727 expected that a CPU will start executing code directly at the right address,
740 for placing the executing secondary CPU in a platform-specific state until the
741 primary CPU performs the necessary actions to bring it out of that state and
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/rk3399_ARM-atf/docs/plat/marvell/armada/
H A Dbuild.rst230 The clock tree configuration preset including CPU and DDR frequency,
233 - CPU_600_DDR_600 - CPU at 600 MHz, DDR at 600 MHz
234 - CPU_800_DDR_800 - CPU at 800 MHz, DDR at 800 MHz
235 - CPU_1000_DDR_800 - CPU at 1000 MHz, DDR at 800 MHz
236 - CPU_1200_DDR_750 - CPU at 1200 MHz, DDR at 750 MHz
238 Look at Armada37x0 chip package marking on board to identify correct CPU frequency.
241 - C080 or I080 - chip with 800 MHz CPU - use ``CLOCKSPRESET=CPU_800_DDR_800``
242 - C100 or I100 - chip with 1000 MHz CPU - use ``CLOCKSPRESET=CPU_1000_DDR_800``
243 - C120 - chip with 1200 MHz CPU - use ``CLOCKSPRESET=CPU_1200_DDR_750``
283 binary and sys-init code from the WTP directory which sets DDR and CPU
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/rk3399_ARM-atf/docs/plat/
H A Dnpcm845x.rst7 The NPCM845X computing subsystem comprises a quadcore Arm Cortex-A35 CPU.
H A Dnvidia-tegra.rst7 T194 has eight NVIDIA Carmel CPU cores in a coherent multi-processor
22 T186 has Dual NVIDIA Denver2 ARM® CPU cores, plus Quad ARM Cortex®-A57 cores,
32 Denver is NVIDIA's own custom-designed, 64-bit, dual-core CPU which is
150 Protection bit, for Arm Cortex-A57 CPUs, during CPU boot. This flag will
/rk3399_ARM-atf/docs/plat/arm/arm_fpga/
H A Dindex.rst22 As the number and topology layout of the CPU cores differs significantly
33 churn. With this option, the code will fall back to some basic CPU support
47 fill the CPU topology nodes. It will also be passed on to BL33, by
60 read-only to the CPU). The FPGA payload tool should be given a text file

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