Lines Matching refs:CPU

1 CPU Reset
4 This document describes the high-level design of the framework to handle CPU
32 Programmable CPU reset address
35 By default, TF-A assumes that the CPU reset address is not programmable.
41 ``RVBAR_EL3``) is programmable then it is possible to make each CPU start directly
54 Cold boot on a single CPU
63 If the platform guarantees that only a single CPU will ever be brought up then
64 no arbitration is required. The notion of primary/secondary CPU itself no longer
67 |Reset code flow with single CPU released out of reset|
77 Programmable CPU reset address, Cold boot on a single CPU
81 a programmable CPU reset address and which release a single CPU out of reset.
85 |Reset code flow with programmable reset address and single CPU released out of reset|
104 BL31 is loaded to its runtime address, which must match the CPU's ``RVBAR_EL3``
117 SRAM and all CPU reset vectors be changed from the default ``0x0`` to this run
136 In the default, unoptimised BL31 reset flow, on a warm boot a CPU is directed
139 CPU executes a modified BL31 initialization, as described below.
144 In this configuration, since the CPU resets to BL31, no parameters are expected
168 .. |Reset code flow with single CPU released out of reset| image:: ../resources/diagrams/reset_code…
169 .. |Reset code flow with programmable reset address and single CPU released out of reset| image:: .…