1*4d9b8281SNishant Sharma/* 2*4d9b8281SNishant Sharma * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved. 3*4d9b8281SNishant Sharma * 4*4d9b8281SNishant Sharma * SPDX-License-Identifier: BSD-3-Clause 5*4d9b8281SNishant Sharma */ 6*4d9b8281SNishant Sharma 7*4d9b8281SNishant Sharma#ifndef RD_V3_DEFS_DTSI 8*4d9b8281SNishant Sharma#define RD_V3_DEFS_DTSI 9*4d9b8281SNishant Sharma 10*4d9b8281SNishant Sharma#define CONCAT(x, y) x##y 11*4d9b8281SNishant Sharma#define CONC(x, y) CONCAT(x, y) 12*4d9b8281SNishant Sharma 13*4d9b8281SNishant Sharma#define ADR(n) \ 14*4d9b8281SNishant Sharma CPU##n:cpu@n##0000 { 15*4d9b8281SNishant Sharma 16*4d9b8281SNishant Sharma#define PRE \ 17*4d9b8281SNishant Sharma device_type = "cpu"; \ 18*4d9b8281SNishant Sharma compatible = "arm,armv8"; 19*4d9b8281SNishant Sharma 20*4d9b8281SNishant Sharma#define CPU_0 \ 21*4d9b8281SNishant Sharma CPU0:cpu@0 { \ 22*4d9b8281SNishant Sharma PRE \ 23*4d9b8281SNishant Sharma reg = <0x0 0x0>;\ 24*4d9b8281SNishant Sharma }; 25*4d9b8281SNishant Sharma 26*4d9b8281SNishant Sharma#define POST }; 27*4d9b8281SNishant Sharma 28*4d9b8281SNishant Sharma/* 29*4d9b8281SNishant Sharma * n - CPU number 30*4d9b8281SNishant Sharma */ 31*4d9b8281SNishant Sharma#define CPU(n) \ 32*4d9b8281SNishant Sharma ADR(n) \ 33*4d9b8281SNishant Sharma PRE \ 34*4d9b8281SNishant Sharma reg = <0x0 CONC(0x, CONC(n, 0000))>; \ 35*4d9b8281SNishant Sharma POST 36*4d9b8281SNishant Sharma 37*4d9b8281SNishant Sharma#endif /* RD_V3_DEFS_DTSI */ 38