rk3399_ARM-atf/docs/porting-guide.rst

99 used to allocate any data structures that are accessed both when a CPU is
131    Defines the normal stack memory available to each CPU. This constant is used
689 For each CPU, the reset vector code is responsible for the following tasks:
693 #. In the case of a cold boot and the CPU being a secondary CPU, ensuring that
694    the CPU is placed in a platform-specific state until the primary CPU
697 #. In the case of a warm boot, ensuring that the CPU jumps to a platform-
714 distinguishing between a warm and cold reset for the current CPU using
727 expected that a CPU will start executing code directly at the right address,
740 for placing the executing secondary CPU in a platform-specific state until the
741 primary CPU performs the necessary actions to bring it out of that state and
744 In the Arm FVP port, when using the normal boot flow, each secondary CPU powers
745 itself off. The primary CPU is responsible for powering up the secondary CPUs
753 primary CPU will execute the cold boot code. Therefore, implementing this
764 This function identifies whether the current CPU is the primary CPU or a
765 secondary CPU. A return value of zero indicates that the CPU is not the
766 primary CPU, while a non-zero return value indicates that the CPU is the
767 primary CPU.
770 primary CPU will execute the cold boot code. Therefore, there is no need to
1105 This function returns the index of the calling CPU which is used as a
1106 CPU-specific linear index into blocks of memory (for example while allocating
1107 per-CPU stacks). This function will be invoked very early in the
1125 This function validates the ``MPIDR`` of a CPU and converts it to an index,
1126 which can be used as a CPU-specific linear index into blocks of memory. In
1130 represents the power domain topology and how this relates to the linear CPU
1271 has been allocated for the current CPU. For BL images that only require a
1272 stack for the primary CPU, the UP version of the function is used. The size
1273 of the stack allocated to each CPU is specified by the platform defined
1289 has been allocated for the current CPU. For BL images that only require a
1290 stack for the primary CPU, the UP version of the function is used. The size
1291 of the stack allocated to each CPU is specified by the platform defined
1307 exception is taken, for example the current exception level, the CPU security
1621 warm boot. For each CPU, BL1 is responsible for the following tasks:
1625 #. In the case of a cold boot and the CPU being the primary CPU, ensuring that
1626    only this CPU executes the remaining BL1 code, including loading and passing
1662 by the primary CPU.
1673    primary CPU.
1889 The BL2 stage is executed only by the primary CPU, which is determined in BL1
1909 by the primary CPU. The 4 arguments are passed by BL1 to BL2 and these arguments
1937 by the primary CPU.
1954 called by the primary CPU.
2023 by the primary CPU. This function receives four parameters which can be used
2046 by the primary CPU.
2070 process and is executed only by the primary CPU. BL1 passes control to BL2U at
2096 called by the primary CPU. The arguments to this function is the address
2115 called by the primary CPU.
2131 called by the primary CPU.
2159 During cold boot, the BL31 stage is executed only by the primary CPU. This is
2199 by the primary CPU. BL2 can pass 4 arguments to BL31 and these arguments are
2226    CPU.
2237 by the primary CPU.
2254 called by the primary CPU.
2266    -  Enable secure interrupts in the GIC CPU interface.
2269       to be signaled to the CPU interface.
2734 frequency for the CPU's generic timer. This value will be programmed into the
2886 *power domain*. A *power domain* is a CPU or a logical group of CPUs which
2888 specified by `PSCI`_. Each CPU in the system is assigned a cpu index which is
2891 *power domain* can be identified in a system by the cpu index of any CPU that
2893 example, a CPU) is at level 0. If the *power domain* node above a CPU is a
2904 CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()``
2905 handler (if present) is called for the CPU power domain.
2929 differently at CPU level versus higher levels. As an example, if the element at
2930 index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down
2947 differently at CPU level versus higher levels. As an example, if the element at
2948 index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down
2964 domain at a particular power domain level. When a CPU wakes up from suspend,
2969 The current CPU is the first CPU in the power domain to resume from the low
2971 CPU in the power domain to suspend and may be needed to calculate the residency
2985 argument) which contains the requested power state for each CPU at a particular
3014 description matches the CPU indices returned by these APIs. These APIs together
3027 called by the primary CPU.
3048 indicated by the passed argument. This provides a fast path for CPU standby
3052 STANDBY and the target power domain level specified should be the CPU. The
3053 handler should put the CPU into a low power retention state (usually by
3060 Perform the platform specific actions to power on a CPU, specified
3068 powering off the calling CPU and its higher parent power domain levels as
3072 for the CPU power domain and its parent power domain levels.
3074 For this handler, the local power state for the CPU power domain will be a
3078 platform thinks that CPU_OFF should not proceed on the calling CPU.
3083 Perform the platform specific actions to prepare to power off the calling CPU
3088 for the CPU power domain and its parent power domain levels. The handler
3092 For this handler, the local power state for the CPU power domain will be a
3129 CPU and its higher parent power domain levels as indicated by the
3135 target local power states for the CPU power domain and its parent
3170 platform specific actions before the CPU is powered down. Since this function is
3172 to the CPU or the platform must ensure that races between multiple CPUs cannot
3177 the CPU power domain and its parent power domain levels.
3180 ``wfi()`` to powerdown the CPU, mitigate any powerdown errata,
3192 This function is called by the PSCI implementation after the calling CPU is
3195 this CPU to enter the normal world and also provide secure runtime firmware
3199 immediately before the CPU was turned on. It indicates which power domains
3200 above the CPU might require initialization due to having previously been in
3207 CPU is fully powered on with respective data caches enabled. The calling CPU and
3219 This function is called by the PSCI implementation after the calling CPU is
3221 event, for example a timer interrupt that was programmed by the CPU during the
3223 setup required to restore the saved state for this CPU to resume execution
3378 appropriately during CPU power down/power up. Any secure interrupt targeted
3379 to the current CPU must be disabled or re-targeted to other running CPU prior
3380 to power down of the current CPU. During power up, these interrupt can be
3381 enabled/re-targeted back to the current CPU.
3403    target CPU of PSCI_CPU_ON API powers up and executes the
3410    called when the CPU wakes up from suspend and executes the
3426    implementation, then it must update the mpidr of the CPU it is resident in
3434    the current CPU ``from_cpu`` (first argument) to another CPU ``to_cpu``
3578 This API is used by the CPU to indicate to the platform IC that processing of
3608 This API is used by the CPU to indicate to the platform IC that processing of
3703 of the CPU to enable quick crash analysis and debugging. This mechanism relies
3903 The second parameter (``cpu_context_t *ctx``) represents the CPU state in the
3938 The second parameter (``cpu_context_t *ctx``) represents the CPU state in the