docs/components/context-management-library.rst

20 with a context management library to handle the context of the CPU, managing the
27 to preserve the state of the CPU at the next lower exception level (EL) in a given
32 In a trusted system at any instance, a given CPU could be executing in one of the
37 If the CPU switches across security states (for example: from Non-secure to Secure
47 that are not influenced by Normal World operations. Therefore, for each CPU, we
49 world do not leak or impact the execution of the CPU in other worlds.
58 This includes implementing CPU context initialization and management routines,
60 firmware, which are collectively referred to as CPU Context Management.
176 #. ``cpu_data.h`` : contains the public interface to Per CPU data structure.
202 CPU Data Structure
204 For a given system, depending on the CPU count, the platform statically
205 allocates memory for the CPU data structure.
212 This CPU data structure has a member element with an array of pointers to hold
230 |CPU Data Structure|
239 percpu_idregs_t idregs[CPU_CONTEXT_NUM] array within the CPU data
243 per-CPU and per-world to accurately represent asymmetric
249 CPU Context and Memory allocation
252 CPU Context
255 state of CPU across exception levels for a given security state are listed below.
284 for each CPU per world is allocated by the world-specific dispatcher components
318 per-CPU data structures, which means that each CPU will have an array of pointers
321 |CPU Context Memory Configuration|
326 The CPU has been assigned context structures for every security state, which include
328 during the bootup of every CPU before they enter any security state for the
330 every CPU context takes place during both cold and warm boot paths.
334 The cold boot path is mainly executed by the primary CPU, other than essential
335 CPU initialization executed by all CPUs. After executing BL1 and BL2, the Primary
336 CPU jumps to the BL31 image for runtime services initialization.
345 management library. At this stage, all Primary CPU contexts are initialized
346 and the CPU exits EL3 to enter the Normal world.
357 During a warm boot sequence, the primary CPU is responsible for powering on the
358 secondary CPUs. Refer to :ref:`CPU Reset` and :ref:`Firmware Design` sections for
363 The primary CPU writes the entrypoint for the secondary CPU. When the secondary
387 The figure above illustrates the same with reference of Primary CPU running at
413 Depending on the security state that the CPU needs to enter, the respective
414 world-specific context setup handlers listed above will be invoked once per-CPU
420 lifetime of EL3 runtime firmware. It is invoked from each CPU via the cold boot
504 Apart from the CPU context structure, we have another structure to manage some
509 individual world. This structure operates independently of the CPU context
538 EL3/Root Context is the execution environment while the CPU is running at EL3.
540 Previously, while the CPU is in execution at EL3, the system registers persist
541 with the values of the incoming world. This implies that if the CPU is entering
562 EL3 Context ensures, CPU executes under fixed EL3 system register settings
587 .. |CPU Context Memory Configuration| image:: ../resources/diagrams/cpu_data_config_context_memory.…
588 .. |CPU Data Structure| image:: ../resources/diagrams/percpu-data-struct.png