| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/reset/ |
| H A D | zynq-reset.txt | 8 - compatible: "xlnx,zynq-reset"
12 - #reset-cells: Must be 1
18 compatible = "xlnx,zynq-reset";
20 #reset-cells = <1>;
25 0 : soft reset
26 32 : ddr reset
27 64 : topsw reset
28 96 : dmac reset
29 128: usb0 reset
30 129: usb1 reset
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| H A D | reset.txt | 3 This binding is intended to represent the hardware reset signals present
8 Hardware blocks typically receive a reset signal. This signal is generated by
9 a reset provider (e.g. power management or clock module) and received by a
10 reset consumer (the module being reset, or a module managing when a sub-
11 ordinate module is reset). This binding exists to represent the provider and
14 A reset signal is represented by the phandle of the provider, plus a reset
15 specifier - a list of DT cells that represents the reset signal within the
16 provider. The length (number of cells) and semantics of the reset specifier
17 are dictated by the binding of the reset provider, although common schemes
20 A word on where to place reset signal consumers in device tree: It is possible
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| H A D | ti-syscon-reset.txt | 4 Almost all SoCs have hardware modules that require reset control in addition
5 to clock and power control for their functionality. The reset control is
13 and provides reset management functionality for various hardware modules
18 Each of the reset provider/controller nodes should be a child of a syscon
27 "ti,syscon-reset"
28 - #reset-cells : Should be 1. Please see the reset consumer node below
30 - ti,reset-bits : Contains the reset control register information
31 Should contain 7 cells for each reset exposed to
33 Cell #1 : offset of the reset assert control
35 Cell #2 : bit position of the reset in the reset
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| H A D | snps,hsdk-reset.txt | 1 Binding for the Synopsys HSDK reset controller
3 This binding uses the common reset binding[1].
5 [1] Documentation/devicetree/bindings/reset/reset.txt
8 - compatible: should be "snps,hsdk-reset".
9 - reg: should always contain 2 pairs address - length: first for reset
10 configuration register and second for corresponding SW reset and status bits
12 - #reset-cells: from common reset binding; Should always be set to 1.
15 reset: reset@880 {
16 compatible = "snps,hsdk-reset";
17 #reset-cells = <1>;
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| H A D | xlnx,zynqmp-reset.txt | 2 = Zynq UltraScale+ MPSoC and Versal reset driver binding =
9 Please also refer to reset.txt in this directory for common reset
13 - compatible: "xlnx,zynqmp-reset" for Zynq UltraScale+ MPSoC platform
14 "xlnx,versal-reset" for Versal platform
15 - #reset-cells: Specifies the number of cells needed to encode reset
27 zynqmp_reset: reset-controller {
28 compatible = "xlnx,zynqmp-reset";
29 #reset-cells = <1>;
34 Specifying reset lines connected to IP modules
37 Device nodes that need access to reset lines should
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| H A D | snps,axs10x-reset.txt | 1 Binding for the AXS10x reset controller
4 to control reset signals of selected peripherals. For example DW GMAC, etc...
6 represents up-to 32 reset lines.
11 This binding uses the common reset binding[1].
13 [1] Documentation/devicetree/bindings/reset/reset.txt
16 - compatible: should be "snps,axs10x-reset".
17 - reg: should always contain pair address - length: for creg reset
19 - #reset-cells: from common reset binding; Should always be set to 1.
22 reset: reset-controller@11220 {
23 compatible = "snps,axs10x-reset";
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| H A D | img,pistachio-reset.txt | 4 This binding describes a reset controller device that is used to enable and
5 disable individual IP blocks within the Pistachio SoC using "soft reset"
8 The actual action taken when soft reset is asserted is hardware dependent.
13 Please refer to Documentation/devicetree/bindings/reset/reset.txt
14 for common reset controller binding usage.
18 - compatible: Contains "img,pistachio-reset"
20 - #reset-cells: Contains 1
31 pistachio_reset: reset-controller {
32 compatible = "img,pistachio-reset";
33 #reset-cells = <1>;
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| H A D | uniphier-reset.txt | 1 UniPhier glue reset controller
4 Peripheral core reset in glue layer
7 Some peripheral core reset belongs to its own glue layer. Before using
8 this core reset, it is necessary to control the clocks and resets to enable
13 "socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC USB3
14 "socionext,uniphier-pro5-usb3-reset" - for Pro5 SoC USB3
15 "socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC USB3
16 "socionext,uniphier-ld20-usb3-reset" - for LD20 SoC USB3
17 "socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC USB3
18 "socionext,uniphier-pro4-ahci-reset" - for Pro4 SoC AHCI
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| H A D | brcm,brcmstb-reset.txt | 1 Broadcom STB SW_INIT-style reset controller
4 Broadcom STB SoCs have a SW_INIT-style reset controller with separate
6 reset lines.
8 Please also refer to reset.txt in this directory for common reset
12 - compatible: should be brcm,brcmstb-reset
14 - #reset-cells: must be set to 1
18 reset: reset-controller@8404318 {
19 compatible = "brcm,brcmstb-reset";
21 #reset-cells = <1>;
25 resets = <&reset 26>;
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| H A D | hisilicon,hi3660-reset.txt | 4 Please also refer to reset.txt in this directory for common reset
7 The reset controller registers are part of the system-ctl block on
12 "hisilicon,hi3660-reset" for HI3660
13 "hisilicon,hi3670-reset", "hisilicon,hi3660-reset" for HI3670
14 - hisi,rst-syscon: phandle of the reset's syscon.
15 - #reset-cells : Specifies the number of cells needed to encode a
16 reset source. The type shall be a <u32> and the value shall be 2.
18 Cell #1 : offset of the reset assert control
22 Cell #2 : bit position of the reset in the reset control register
31 compatible = "hisilicon,hi3660-reset";
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| H A D | nuvoton,npcm-reset.txt | 4 - compatible : "nuvoton,npcm750-reset" for NPCM7XX BMC
6 - #reset-cells: must be set to 2
9 - nuvoton,sw-reset-number - Contains the software reset number to restart the SoC.
10 NPCM7xx contain four software reset that represent numbers 1 to 4.
12 If 'nuvoton,sw-reset-number' is not specified software reset is disabled.
16 compatible = "nuvoton,npcm750-reset";
18 #reset-cells = <2>;
19 nuvoton,sw-reset-number = <2>;
22 Specifying reset lines connected to IP NPCM7XX modules
32 The index could be found in <dt-bindings/reset/nuvoton,npcm7xx-reset.h>.
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| H A D | lantiq,reset.txt | 1 Lantiq XWAY SoC RCU reset controller binding
4 This binding describes a reset-controller found on the RCU module on Lantiq
12 "lantiq,danube-reset"
13 "lantiq,xrx200-reset"
16 - Offset of the reset set register
17 - Offset of the reset status register
18 - #reset-cells : Specifies the number of cells needed to encode the
19 reset line, should be 2.
20 The first cell takes the reset set bit and the
24 Example for the reset-controllers on the xRX200 SoCs:
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| /OK3568_Linux_fs/kernel/drivers/reset/ |
| H A D | Makefile | 6 obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
7 obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
8 obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o
9 obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
10 obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o
11 obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o
12 obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
13 obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
14 obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o
15 obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
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| H A D | Kconfig | 11 This framework is designed to abstract reset handling of devices
12 via GPIOs or SoC-internal reset controller modules.
22 This option enables support for the external reset functions for
29 This enables the ATH79 reset controller driver that supports the
30 AR71xx SoC reset controller.
36 This enables the reset controller driver for AXS10x.
42 This enables the reset controller driver for Marvell Berlin SoCs.
45 tristate "Broadcom STB reset controller"
49 This enables the reset controller driver for Broadcom STB SoCs using
53 bool "Broadcom STB RESCAL reset controller"
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| /OK3568_Linux_fs/u-boot/doc/device-tree-bindings/reset/ |
| H A D | reset.txt | 3 This binding is intended to represent the hardware reset signals present
8 Hardware blocks typically receive a reset signal. This signal is generated by
9 a reset provider (e.g. power management or clock module) and received by a
10 reset consumer (the module being reset, or a module managing when a sub-
11 ordinate module is reset). This binding exists to represent the provider and
14 A reset signal is represented by the phandle of the provider, plus a reset
15 specifier - a list of DT cells that represents the reset signal within the
16 provider. The length (number of cells) and semantics of the reset specifier
17 are dictated by the binding of the reset provider, although common schemes
20 A word on where to place reset signal consumers in device tree: It is possible
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| /OK3568_Linux_fs/u-boot/spl/drivers/reset/ |
| H A D | reset-uclass.su | |
| /OK3568_Linux_fs/u-boot/drivers/reset/ |
| H A D | reset-uclass.su | |
| H A D | Kconfig | 4 bool "Enable reset controllers using Driver Model"
7 Enable support for the reset controller driver class. Many hardware
8 modules are equipped with a reset signal, typically driven by some
9 reset controller hardware module within the chip. In U-Boot, reset
10 controller drivers allow control over these reset signals. In some
12 although driving such reset isgnals using GPIOs may be more
16 bool "Enable reset controllers using Driver Model in SPL"
19 Enable support for the reset controller driver class. Many hardware
20 modules are equipped with a reset signal, typically driven by some
21 reset controller hardware module within the chip. In U-Boot, reset
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| /OK3568_Linux_fs/kernel/drivers/power/reset/ |
| H A D | at91-reset.c | 70 struct at91_reset *reset = container_of(this, struct at91_reset, nb); in at91_reset() local
93 : "r" (reset->ramc_base[0]), in at91_reset()
94 "r" (reset->ramc_base[1]), in at91_reset()
95 "r" (reset->rstc_base), in at91_reset()
98 "r" (reset->args), in at91_reset()
99 "r" (reset->ramc_lpr) in at91_reset()
187 struct at91_reset *reset; in at91_reset_probe() local
191 reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL); in at91_reset_probe()
192 if (!reset) in at91_reset_probe()
195 reset->rstc_base = of_iomap(pdev->dev.of_node, 0); in at91_reset_probe()
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| /OK3568_Linux_fs/kernel/drivers/soc/ti/ |
| H A D | omap_prm.c | 407 static bool _is_valid_reset(struct omap_reset_data *reset, unsigned long id) in _is_valid_reset() argument
409 if (reset->mask & BIT(id)) in _is_valid_reset()
415 static int omap_reset_get_st_bit(struct omap_reset_data *reset, in omap_reset_get_st_bit() argument
418 const struct omap_rst_map *map = reset->prm->data->rstmap; in omap_reset_get_st_bit()
433 struct omap_reset_data *reset = to_omap_reset_data(rcdev); in omap_reset_status() local
435 int st_bit = omap_reset_get_st_bit(reset, id); in omap_reset_status()
436 bool has_rstst = reset->prm->data->rstst || in omap_reset_status()
437 (reset->prm->data->flags & OMAP_PRM_HAS_RSTST); in omap_reset_status()
444 v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl); in omap_reset_status()
452 v = readl_relaxed(reset->prm->base + reset->prm->data->rstst); in omap_reset_status()
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| /OK3568_Linux_fs/kernel/drivers/gpu/arm/bifrost/csf/ |
| H A D | mali_kbase_csf_reset_gpu.c | 101 down_read(&kbdev->csf.reset.sem); in kbase_reset_gpu_prevent_and_wait()
103 if (atomic_read(&kbdev->csf.reset.state) == in kbase_reset_gpu_prevent_and_wait()
105 up_read(&kbdev->csf.reset.sem); in kbase_reset_gpu_prevent_and_wait()
110 up_read(&kbdev->csf.reset.sem); in kbase_reset_gpu_prevent_and_wait()
120 if (!down_read_trylock(&kbdev->csf.reset.sem)) in kbase_reset_gpu_try_prevent()
123 if (atomic_read(&kbdev->csf.reset.state) == in kbase_reset_gpu_try_prevent()
125 up_read(&kbdev->csf.reset.sem); in kbase_reset_gpu_try_prevent()
130 up_read(&kbdev->csf.reset.sem); in kbase_reset_gpu_try_prevent()
139 up_read(&kbdev->csf.reset.sem); in kbase_reset_gpu_allow()
146 lockdep_assert_held_read(&kbdev->csf.reset.sem); in kbase_reset_gpu_assert_prevented()
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/power/reset/ |
| H A D | keystone-reset.txt | 1 * Device tree bindings for Texas Instruments keystone reset
3 This node is intended to allow SoC reset in case of software reset
6 The Keystone SoCs can contain up to 4 watchdog timers to reset
8 block. The Reset Mux block can be configured to cause reset or not.
10 Additionally soft or hard reset can be configured.
14 - compatible: ti,keystone-reset
18 reset control registers.
26 - ti,soft-reset: Boolean option indicating soft reset.
27 By default hard reset is used.
29 - ti,wdt-list: WDT list that can cause SoC reset. It's not related
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| /OK3568_Linux_fs/u-boot/drivers/sysreset/ |
| H A D | Kconfig | 2 # System reset devices
5 menu "System reset device drivers"
8 bool "Enable support for system reset drivers"
11 Enable system reset drivers which can be used to reset the CPU or
12 board. Each driver can provide a reset method which will be called
13 to effect a reset. The uclass will try all available drivers when
17 bool "Enable support for system reset drivers in SPL mode"
20 Enable system reset drivers which can be used to reset the CPU or
21 board. Each driver can provide a reset method which will be called
22 to effect a reset. The uclass will try all available drivers when
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/ |
| H A D | qcom,pcie.txt | 148 Definition: List of phandle and reset specifier pairs as listed
149 in reset-names property
151 - reset-names:
155 - "axi" AXI reset
156 - "ahb" AHB reset
157 - "por" POR reset
158 - "pci" PCI reset
159 - "phy" PHY reset
161 - reset-names:
165 - "core" Core reset
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| /OK3568_Linux_fs/u-boot/doc/device-tree-bindings/gpu/ |
| H A D | nvidia,tegra20-host1x.txt | 14 - resets: Must contain an entry for each entry in reset-names.
15 See ../reset/reset.txt for details.
16 - reset-names: Must include the following entries:
30 - resets: Must contain an entry for each entry in reset-names.
31 See ../reset/reset.txt for details.
32 - reset-names: Must include the following entries:
43 - resets: Must contain an entry for each entry in reset-names.
44 See ../reset/reset.txt for details.
45 - reset-names: Must include the following entries:
56 - resets: Must contain an entry for each entry in reset-names.
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