1*4882a593SmuzhiyunLantiq XWAY SoC RCU reset controller binding 2*4882a593Smuzhiyun============================================ 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThis binding describes a reset-controller found on the RCU module on Lantiq 5*4882a593SmuzhiyunXWAY SoCs. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunThis node has to be a sub node of the Lantiq RCU block. 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun------------------------------------------------------------------------------- 10*4882a593SmuzhiyunRequired properties: 11*4882a593Smuzhiyun- compatible : Should be one of 12*4882a593Smuzhiyun "lantiq,danube-reset" 13*4882a593Smuzhiyun "lantiq,xrx200-reset" 14*4882a593Smuzhiyun- reg : Defines the following sets of registers in the parent 15*4882a593Smuzhiyun syscon device 16*4882a593Smuzhiyun - Offset of the reset set register 17*4882a593Smuzhiyun - Offset of the reset status register 18*4882a593Smuzhiyun- #reset-cells : Specifies the number of cells needed to encode the 19*4882a593Smuzhiyun reset line, should be 2. 20*4882a593Smuzhiyun The first cell takes the reset set bit and the 21*4882a593Smuzhiyun second cell takes the status bit. 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun------------------------------------------------------------------------------- 24*4882a593SmuzhiyunExample for the reset-controllers on the xRX200 SoCs: 25*4882a593Smuzhiyun reset0: reset-controller@10 { 26*4882a593Smuzhiyun compatible = "lantiq,xrx200-reset"; 27*4882a593Smuzhiyun reg <0x10 0x04>, <0x14 0x04>; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #reset-cells = <2>; 30*4882a593Smuzhiyun }; 31