1*4882a593SmuzhiyunXilinx Zynq Reset Manager 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe Zynq AP-SoC has several different resets. 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunSee Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties: 8*4882a593Smuzhiyun- compatible: "xlnx,zynq-reset" 9*4882a593Smuzhiyun- reg: SLCR offset and size taken via syscon <0x200 0x48> 10*4882a593Smuzhiyun- syscon: <&slcr> 11*4882a593Smuzhiyun This should be a phandle to the Zynq's SLCR registers. 12*4882a593Smuzhiyun- #reset-cells: Must be 1 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunThe Zynq Reset Manager needs to be a childnode of the SLCR. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunExample: 17*4882a593Smuzhiyun rstc: rstc@200 { 18*4882a593Smuzhiyun compatible = "xlnx,zynq-reset"; 19*4882a593Smuzhiyun reg = <0x200 0x48>; 20*4882a593Smuzhiyun #reset-cells = <1>; 21*4882a593Smuzhiyun syscon = <&slcr>; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunReset outputs: 25*4882a593Smuzhiyun 0 : soft reset 26*4882a593Smuzhiyun 32 : ddr reset 27*4882a593Smuzhiyun 64 : topsw reset 28*4882a593Smuzhiyun 96 : dmac reset 29*4882a593Smuzhiyun 128: usb0 reset 30*4882a593Smuzhiyun 129: usb1 reset 31*4882a593Smuzhiyun 160: gem0 reset 32*4882a593Smuzhiyun 161: gem1 reset 33*4882a593Smuzhiyun 164: gem0 rx reset 34*4882a593Smuzhiyun 165: gem1 rx reset 35*4882a593Smuzhiyun 166: gem0 ref reset 36*4882a593Smuzhiyun 167: gem1 ref reset 37*4882a593Smuzhiyun 192: sdio0 reset 38*4882a593Smuzhiyun 193: sdio1 reset 39*4882a593Smuzhiyun 196: sdio0 ref reset 40*4882a593Smuzhiyun 197: sdio1 ref reset 41*4882a593Smuzhiyun 224: spi0 reset 42*4882a593Smuzhiyun 225: spi1 reset 43*4882a593Smuzhiyun 226: spi0 ref reset 44*4882a593Smuzhiyun 227: spi1 ref reset 45*4882a593Smuzhiyun 256: can0 reset 46*4882a593Smuzhiyun 257: can1 reset 47*4882a593Smuzhiyun 258: can0 ref reset 48*4882a593Smuzhiyun 259: can1 ref reset 49*4882a593Smuzhiyun 288: i2c0 reset 50*4882a593Smuzhiyun 289: i2c1 reset 51*4882a593Smuzhiyun 320: uart0 reset 52*4882a593Smuzhiyun 321: uart1 reset 53*4882a593Smuzhiyun 322: uart0 ref reset 54*4882a593Smuzhiyun 323: uart1 ref reset 55*4882a593Smuzhiyun 352: gpio reset 56*4882a593Smuzhiyun 384: lqspi reset 57*4882a593Smuzhiyun 385: qspi ref reset 58*4882a593Smuzhiyun 416: smc reset 59*4882a593Smuzhiyun 417: smc ref reset 60*4882a593Smuzhiyun 448: ocm reset 61*4882a593Smuzhiyun 512: fpga0 out reset 62*4882a593Smuzhiyun 513: fpga1 out reset 63*4882a593Smuzhiyun 514: fpga2 out reset 64*4882a593Smuzhiyun 515: fpga3 out reset 65*4882a593Smuzhiyun 544: a9 reset 0 66*4882a593Smuzhiyun 545: a9 reset 1 67*4882a593Smuzhiyun 552: peri reset 68*4882a593Smuzhiyun 69