xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593SmuzhiyunTI SysCon Reset Controller
2*4882a593Smuzhiyun=======================
3*4882a593Smuzhiyun
4*4882a593SmuzhiyunAlmost all SoCs have hardware modules that require reset control in addition
5*4882a593Smuzhiyunto clock and power control for their functionality. The reset control is
6*4882a593Smuzhiyuntypically provided by means of memory-mapped I/O registers. These registers are
7*4882a593Smuzhiyunsometimes a part of a larger register space region implementing various
8*4882a593Smuzhiyunfunctionalities. This register range is best represented as a syscon node to
9*4882a593Smuzhiyunallow multiple entities to access their relevant registers in the common
10*4882a593Smuzhiyunregister space.
11*4882a593Smuzhiyun
12*4882a593SmuzhiyunA SysCon Reset Controller node defines a device that uses a syscon node
13*4882a593Smuzhiyunand provides reset management functionality for various hardware modules
14*4882a593Smuzhiyunpresent on the SoC.
15*4882a593Smuzhiyun
16*4882a593SmuzhiyunSysCon Reset Controller Node
17*4882a593Smuzhiyun============================
18*4882a593SmuzhiyunEach of the reset provider/controller nodes should be a child of a syscon
19*4882a593Smuzhiyunnode and have the following properties.
20*4882a593Smuzhiyun
21*4882a593SmuzhiyunRequired properties:
22*4882a593Smuzhiyun--------------------
23*4882a593Smuzhiyun - compatible		: Should be,
24*4882a593Smuzhiyun			    "ti,k2e-pscrst"
25*4882a593Smuzhiyun			    "ti,k2l-pscrst"
26*4882a593Smuzhiyun			    "ti,k2hk-pscrst"
27*4882a593Smuzhiyun			    "ti,syscon-reset"
28*4882a593Smuzhiyun - #reset-cells		: Should be 1. Please see the reset consumer node below
29*4882a593Smuzhiyun			  for usage details
30*4882a593Smuzhiyun - ti,reset-bits	: Contains the reset control register information
31*4882a593Smuzhiyun			  Should contain 7 cells for each reset exposed to
32*4882a593Smuzhiyun			  consumers, defined as:
33*4882a593Smuzhiyun			    Cell #1 : offset of the reset assert control
34*4882a593Smuzhiyun			              register from the syscon register base
35*4882a593Smuzhiyun			    Cell #2 : bit position of the reset in the reset
36*4882a593Smuzhiyun			              assert control register
37*4882a593Smuzhiyun			    Cell #3 : offset of the reset deassert control
38*4882a593Smuzhiyun			              register from the syscon register base
39*4882a593Smuzhiyun			    Cell #4 : bit position of the reset in the reset
40*4882a593Smuzhiyun			              deassert control register
41*4882a593Smuzhiyun			    Cell #5 : offset of the reset status register
42*4882a593Smuzhiyun			              from the syscon register base
43*4882a593Smuzhiyun			    Cell #6 : bit position of the reset in the
44*4882a593Smuzhiyun			              reset status register
45*4882a593Smuzhiyun			    Cell #7 : Flags used to control reset behavior,
46*4882a593Smuzhiyun			              availible flags defined in the DT include
47*4882a593Smuzhiyun			              file <dt-bindings/reset/ti-syscon.h>
48*4882a593Smuzhiyun
49*4882a593SmuzhiyunSysCon Reset Consumer Nodes
50*4882a593Smuzhiyun===========================
51*4882a593SmuzhiyunEach of the reset consumer nodes should have the following properties,
52*4882a593Smuzhiyunin addition to their own properties.
53*4882a593Smuzhiyun
54*4882a593SmuzhiyunRequired properties:
55*4882a593Smuzhiyun--------------------
56*4882a593Smuzhiyun - resets	: A phandle to the reset controller node and an index number
57*4882a593Smuzhiyun		  to a reset specifier as defined above.
58*4882a593Smuzhiyun
59*4882a593SmuzhiyunPlease also refer to Documentation/devicetree/bindings/reset/reset.txt for
60*4882a593Smuzhiyuncommon reset controller usage by consumers.
61*4882a593Smuzhiyun
62*4882a593SmuzhiyunExample:
63*4882a593Smuzhiyun--------
64*4882a593SmuzhiyunThe following example demonstrates a syscon node, the reset controller node
65*4882a593Smuzhiyunusing the syscon node, and a consumer (a DSP device) on the TI Keystone 2
66*4882a593Smuzhiyun66AK2E SoC.
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun/ {
69*4882a593Smuzhiyun	soc {
70*4882a593Smuzhiyun		psc: power-sleep-controller@2350000 {
71*4882a593Smuzhiyun			compatible = "syscon", "simple-mfd";
72*4882a593Smuzhiyun			reg = <0x02350000 0x1000>;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun			pscrst: reset-controller {
75*4882a593Smuzhiyun				compatible = "ti,k2e-pscrst", "ti,syscon-reset";
76*4882a593Smuzhiyun				#reset-cells = <1>;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun				ti,reset-bits = <
79*4882a593Smuzhiyun					0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET   | STATUS_CLEAR) /* 0: dsp0 */
80*4882a593Smuzhiyun					0xa40 5 0xa44 3 0     0 (ASSERT_SET   | DEASSERT_CLEAR | STATUS_NONE)  /* 1: example */
81*4882a593Smuzhiyun				>;
82*4882a593Smuzhiyun			};
83*4882a593Smuzhiyun		};
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun		dsp0: dsp0 {
86*4882a593Smuzhiyun			...
87*4882a593Smuzhiyun			resets = <&pscrst 0>;
88*4882a593Smuzhiyun			...
89*4882a593Smuzhiyun		};
90*4882a593Smuzhiyun	};
91*4882a593Smuzhiyun};
92