xref: /OK3568_Linux_fs/kernel/drivers/reset/Kconfig (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyunconfig ARCH_HAS_RESET_CONTROLLER
3*4882a593Smuzhiyun	bool
4*4882a593Smuzhiyun
5*4882a593Smuzhiyunmenuconfig RESET_CONTROLLER
6*4882a593Smuzhiyun	bool "Reset Controller Support"
7*4882a593Smuzhiyun	default y if ARCH_HAS_RESET_CONTROLLER
8*4882a593Smuzhiyun	help
9*4882a593Smuzhiyun	  Generic Reset Controller support.
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun	  This framework is designed to abstract reset handling of devices
12*4882a593Smuzhiyun	  via GPIOs or SoC-internal reset controller modules.
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun	  If unsure, say no.
15*4882a593Smuzhiyun
16*4882a593Smuzhiyunif RESET_CONTROLLER
17*4882a593Smuzhiyun
18*4882a593Smuzhiyunconfig RESET_A10SR
19*4882a593Smuzhiyun	tristate "Altera Arria10 System Resource Reset"
20*4882a593Smuzhiyun	depends on MFD_ALTERA_A10SR
21*4882a593Smuzhiyun	help
22*4882a593Smuzhiyun	  This option enables support for the external reset functions for
23*4882a593Smuzhiyun	  peripheral PHYs on the Altera Arria10 System Resource Chip.
24*4882a593Smuzhiyun
25*4882a593Smuzhiyunconfig RESET_ATH79
26*4882a593Smuzhiyun	bool "AR71xx Reset Driver" if COMPILE_TEST
27*4882a593Smuzhiyun	default ATH79
28*4882a593Smuzhiyun	help
29*4882a593Smuzhiyun	  This enables the ATH79 reset controller driver that supports the
30*4882a593Smuzhiyun	  AR71xx SoC reset controller.
31*4882a593Smuzhiyun
32*4882a593Smuzhiyunconfig RESET_AXS10X
33*4882a593Smuzhiyun	bool "AXS10x Reset Driver" if COMPILE_TEST
34*4882a593Smuzhiyun	default ARC_PLAT_AXS10X
35*4882a593Smuzhiyun	help
36*4882a593Smuzhiyun	  This enables the reset controller driver for AXS10x.
37*4882a593Smuzhiyun
38*4882a593Smuzhiyunconfig RESET_BERLIN
39*4882a593Smuzhiyun	bool "Berlin Reset Driver" if COMPILE_TEST
40*4882a593Smuzhiyun	default ARCH_BERLIN
41*4882a593Smuzhiyun	help
42*4882a593Smuzhiyun	  This enables the reset controller driver for Marvell Berlin SoCs.
43*4882a593Smuzhiyun
44*4882a593Smuzhiyunconfig RESET_BRCMSTB
45*4882a593Smuzhiyun	tristate "Broadcom STB reset controller"
46*4882a593Smuzhiyun	depends on ARCH_BRCMSTB || COMPILE_TEST
47*4882a593Smuzhiyun	default ARCH_BRCMSTB
48*4882a593Smuzhiyun	help
49*4882a593Smuzhiyun	  This enables the reset controller driver for Broadcom STB SoCs using
50*4882a593Smuzhiyun	  a SUN_TOP_CTRL_SW_INIT style controller.
51*4882a593Smuzhiyun
52*4882a593Smuzhiyunconfig RESET_BRCMSTB_RESCAL
53*4882a593Smuzhiyun	bool "Broadcom STB RESCAL reset controller"
54*4882a593Smuzhiyun	depends on HAS_IOMEM
55*4882a593Smuzhiyun	depends on ARCH_BRCMSTB || COMPILE_TEST
56*4882a593Smuzhiyun	default ARCH_BRCMSTB
57*4882a593Smuzhiyun	help
58*4882a593Smuzhiyun	  This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on
59*4882a593Smuzhiyun	  BCM7216.
60*4882a593Smuzhiyun
61*4882a593Smuzhiyunconfig RESET_HSDK
62*4882a593Smuzhiyun	bool "Synopsys HSDK Reset Driver"
63*4882a593Smuzhiyun	depends on HAS_IOMEM
64*4882a593Smuzhiyun	depends on ARC_SOC_HSDK || COMPILE_TEST
65*4882a593Smuzhiyun	help
66*4882a593Smuzhiyun	  This enables the reset controller driver for HSDK board.
67*4882a593Smuzhiyun
68*4882a593Smuzhiyunconfig RESET_IMX7
69*4882a593Smuzhiyun	tristate "i.MX7/8 Reset Driver"
70*4882a593Smuzhiyun	depends on HAS_IOMEM
71*4882a593Smuzhiyun	depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST
72*4882a593Smuzhiyun	default y if SOC_IMX7D
73*4882a593Smuzhiyun	select MFD_SYSCON
74*4882a593Smuzhiyun	help
75*4882a593Smuzhiyun	  This enables the reset controller driver for i.MX7 SoCs.
76*4882a593Smuzhiyun
77*4882a593Smuzhiyunconfig RESET_INTEL_GW
78*4882a593Smuzhiyun	bool "Intel Reset Controller Driver"
79*4882a593Smuzhiyun	depends on X86 || COMPILE_TEST
80*4882a593Smuzhiyun	depends on OF && HAS_IOMEM
81*4882a593Smuzhiyun	select REGMAP_MMIO
82*4882a593Smuzhiyun	help
83*4882a593Smuzhiyun	  This enables the reset controller driver for Intel Gateway SoCs.
84*4882a593Smuzhiyun	  Say Y to control the reset signals provided by reset controller.
85*4882a593Smuzhiyun	  Otherwise, say N.
86*4882a593Smuzhiyun
87*4882a593Smuzhiyunconfig RESET_LANTIQ
88*4882a593Smuzhiyun	bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
89*4882a593Smuzhiyun	default SOC_TYPE_XWAY
90*4882a593Smuzhiyun	help
91*4882a593Smuzhiyun	  This enables the reset controller driver for Lantiq / Intel XWAY SoCs.
92*4882a593Smuzhiyun
93*4882a593Smuzhiyunconfig RESET_LPC18XX
94*4882a593Smuzhiyun	bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST
95*4882a593Smuzhiyun	default ARCH_LPC18XX
96*4882a593Smuzhiyun	help
97*4882a593Smuzhiyun	  This enables the reset controller driver for NXP LPC18xx/43xx SoCs.
98*4882a593Smuzhiyun
99*4882a593Smuzhiyunconfig RESET_MESON
100*4882a593Smuzhiyun	tristate "Meson Reset Driver"
101*4882a593Smuzhiyun	depends on ARCH_MESON || COMPILE_TEST
102*4882a593Smuzhiyun	default ARCH_MESON
103*4882a593Smuzhiyun	help
104*4882a593Smuzhiyun	  This enables the reset driver for Amlogic Meson SoCs.
105*4882a593Smuzhiyun
106*4882a593Smuzhiyunconfig RESET_MESON_AUDIO_ARB
107*4882a593Smuzhiyun	tristate "Meson Audio Memory Arbiter Reset Driver"
108*4882a593Smuzhiyun	depends on ARCH_MESON || COMPILE_TEST
109*4882a593Smuzhiyun	help
110*4882a593Smuzhiyun	  This enables the reset driver for Audio Memory Arbiter of
111*4882a593Smuzhiyun	  Amlogic's A113 based SoCs
112*4882a593Smuzhiyun
113*4882a593Smuzhiyunconfig RESET_NPCM
114*4882a593Smuzhiyun	bool "NPCM BMC Reset Driver" if COMPILE_TEST
115*4882a593Smuzhiyun	default ARCH_NPCM
116*4882a593Smuzhiyun	help
117*4882a593Smuzhiyun	  This enables the reset controller driver for Nuvoton NPCM
118*4882a593Smuzhiyun	  BMC SoCs.
119*4882a593Smuzhiyun
120*4882a593Smuzhiyunconfig RESET_OXNAS
121*4882a593Smuzhiyun	bool
122*4882a593Smuzhiyun
123*4882a593Smuzhiyunconfig RESET_PISTACHIO
124*4882a593Smuzhiyun	bool "Pistachio Reset Driver" if COMPILE_TEST
125*4882a593Smuzhiyun	default MACH_PISTACHIO
126*4882a593Smuzhiyun	help
127*4882a593Smuzhiyun	  This enables the reset driver for ImgTec Pistachio SoCs.
128*4882a593Smuzhiyun
129*4882a593Smuzhiyunconfig RESET_QCOM_AOSS
130*4882a593Smuzhiyun	tristate "Qcom AOSS Reset Driver"
131*4882a593Smuzhiyun	depends on ARCH_QCOM || COMPILE_TEST
132*4882a593Smuzhiyun	help
133*4882a593Smuzhiyun	  This enables the AOSS (always on subsystem) reset driver
134*4882a593Smuzhiyun	  for Qualcomm SDM845 SoCs. Say Y if you want to control
135*4882a593Smuzhiyun	  reset signals provided by AOSS for Modem, Venus, ADSP,
136*4882a593Smuzhiyun	  GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
137*4882a593Smuzhiyun
138*4882a593Smuzhiyunconfig RESET_QCOM_PDC
139*4882a593Smuzhiyun	tristate "Qualcomm PDC Reset Driver"
140*4882a593Smuzhiyun	depends on ARCH_QCOM || COMPILE_TEST
141*4882a593Smuzhiyun	help
142*4882a593Smuzhiyun	  This enables the PDC (Power Domain Controller) reset driver
143*4882a593Smuzhiyun	  for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want
144*4882a593Smuzhiyun	  to control reset signals provided by PDC for Modem, Compute,
145*4882a593Smuzhiyun	  Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
146*4882a593Smuzhiyun
147*4882a593Smuzhiyunconfig RESET_RASPBERRYPI
148*4882a593Smuzhiyun	tristate "Raspberry Pi 4 Firmware Reset Driver"
149*4882a593Smuzhiyun	depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST)
150*4882a593Smuzhiyun	default USB_XHCI_PCI
151*4882a593Smuzhiyun	help
152*4882a593Smuzhiyun	  Raspberry Pi 4's co-processor controls some of the board's HW
153*4882a593Smuzhiyun	  initialization process, but it's up to Linux to trigger it when
154*4882a593Smuzhiyun	  relevant. This driver provides a reset controller capable of
155*4882a593Smuzhiyun	  interfacing with RPi4's co-processor and model these firmware
156*4882a593Smuzhiyun	  initialization routines as reset lines.
157*4882a593Smuzhiyun
158*4882a593Smuzhiyunconfig RESET_SCMI
159*4882a593Smuzhiyun	tristate "Reset driver controlled via ARM SCMI interface"
160*4882a593Smuzhiyun	depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
161*4882a593Smuzhiyun	default ARM_SCMI_PROTOCOL
162*4882a593Smuzhiyun	help
163*4882a593Smuzhiyun	  This driver provides support for reset signal/domains that are
164*4882a593Smuzhiyun	  controlled by firmware that implements the SCMI interface.
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun	  This driver uses SCMI Message Protocol to interact with the
167*4882a593Smuzhiyun	  firmware controlling all the reset signals.
168*4882a593Smuzhiyun
169*4882a593Smuzhiyunconfig RESET_SIMPLE
170*4882a593Smuzhiyun	bool "Simple Reset Controller Driver" if COMPILE_TEST
171*4882a593Smuzhiyun	default ARCH_AGILEX || ARCH_ASPEED || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARC
172*4882a593Smuzhiyun	help
173*4882a593Smuzhiyun	  This enables a simple reset controller driver for reset lines that
174*4882a593Smuzhiyun	  that can be asserted and deasserted by toggling bits in a contiguous,
175*4882a593Smuzhiyun	  exclusive register space.
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun	  Currently this driver supports:
178*4882a593Smuzhiyun	   - Altera SoCFPGAs
179*4882a593Smuzhiyun	   - ASPEED BMC SoCs
180*4882a593Smuzhiyun	   - Bitmain BM1880 SoC
181*4882a593Smuzhiyun	   - Realtek SoCs
182*4882a593Smuzhiyun	   - RCC reset controller in STM32 MCUs
183*4882a593Smuzhiyun	   - Allwinner SoCs
184*4882a593Smuzhiyun	   - ZTE's zx2967 family
185*4882a593Smuzhiyun
186*4882a593Smuzhiyunconfig RESET_STM32MP157
187*4882a593Smuzhiyun	bool "STM32MP157 Reset Driver" if COMPILE_TEST
188*4882a593Smuzhiyun	default MACH_STM32MP157
189*4882a593Smuzhiyun	help
190*4882a593Smuzhiyun	  This enables the RCC reset controller driver for STM32 MPUs.
191*4882a593Smuzhiyun
192*4882a593Smuzhiyunconfig RESET_SOCFPGA
193*4882a593Smuzhiyun	bool "SoCFPGA Reset Driver" if COMPILE_TEST && !ARCH_SOCFPGA
194*4882a593Smuzhiyun	default ARCH_SOCFPGA
195*4882a593Smuzhiyun	select RESET_SIMPLE
196*4882a593Smuzhiyun	help
197*4882a593Smuzhiyun	  This enables the reset driver for the SoCFPGA ARMv7 platforms. This
198*4882a593Smuzhiyun	  driver gets initialized early during platform init calls.
199*4882a593Smuzhiyun
200*4882a593Smuzhiyunconfig RESET_SUNXI
201*4882a593Smuzhiyun	bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
202*4882a593Smuzhiyun	default ARCH_SUNXI
203*4882a593Smuzhiyun	select RESET_SIMPLE
204*4882a593Smuzhiyun	help
205*4882a593Smuzhiyun	  This enables the reset driver for Allwinner SoCs.
206*4882a593Smuzhiyun
207*4882a593Smuzhiyunconfig RESET_TI_SCI
208*4882a593Smuzhiyun	tristate "TI System Control Interface (TI-SCI) reset driver"
209*4882a593Smuzhiyun	depends on TI_SCI_PROTOCOL
210*4882a593Smuzhiyun	help
211*4882a593Smuzhiyun	  This enables the reset driver support over TI System Control Interface
212*4882a593Smuzhiyun	  available on some new TI's SoCs. If you wish to use reset resources
213*4882a593Smuzhiyun	  managed by the TI System Controller, say Y here. Otherwise, say N.
214*4882a593Smuzhiyun
215*4882a593Smuzhiyunconfig RESET_TI_SYSCON
216*4882a593Smuzhiyun	tristate "TI SYSCON Reset Driver"
217*4882a593Smuzhiyun	depends on HAS_IOMEM
218*4882a593Smuzhiyun	select MFD_SYSCON
219*4882a593Smuzhiyun	help
220*4882a593Smuzhiyun	  This enables the reset driver support for TI devices with
221*4882a593Smuzhiyun	  memory-mapped reset registers as part of a syscon device node. If
222*4882a593Smuzhiyun	  you wish to use the reset framework for such memory-mapped devices,
223*4882a593Smuzhiyun	  say Y here. Otherwise, say N.
224*4882a593Smuzhiyun
225*4882a593Smuzhiyunconfig RESET_UNIPHIER
226*4882a593Smuzhiyun	tristate "Reset controller driver for UniPhier SoCs"
227*4882a593Smuzhiyun	depends on ARCH_UNIPHIER || COMPILE_TEST
228*4882a593Smuzhiyun	depends on OF && MFD_SYSCON
229*4882a593Smuzhiyun	default ARCH_UNIPHIER
230*4882a593Smuzhiyun	help
231*4882a593Smuzhiyun	  Support for reset controllers on UniPhier SoCs.
232*4882a593Smuzhiyun	  Say Y if you want to control reset signals provided by System Control
233*4882a593Smuzhiyun	  block, Media I/O block, Peripheral Block.
234*4882a593Smuzhiyun
235*4882a593Smuzhiyunconfig RESET_UNIPHIER_GLUE
236*4882a593Smuzhiyun	tristate "Reset driver in glue layer for UniPhier SoCs"
237*4882a593Smuzhiyun	depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF
238*4882a593Smuzhiyun	default ARCH_UNIPHIER
239*4882a593Smuzhiyun	select RESET_SIMPLE
240*4882a593Smuzhiyun	help
241*4882a593Smuzhiyun	  Support for peripheral core reset included in its own glue layer
242*4882a593Smuzhiyun	  on UniPhier SoCs. Say Y if you want to control reset signals
243*4882a593Smuzhiyun	  provided by the glue layer.
244*4882a593Smuzhiyun
245*4882a593Smuzhiyunconfig RESET_ZYNQ
246*4882a593Smuzhiyun	bool "ZYNQ Reset Driver" if COMPILE_TEST
247*4882a593Smuzhiyun	default ARCH_ZYNQ
248*4882a593Smuzhiyun	help
249*4882a593Smuzhiyun	  This enables the reset controller driver for Xilinx Zynq SoCs.
250*4882a593Smuzhiyun
251*4882a593Smuzhiyunsource "drivers/reset/sti/Kconfig"
252*4882a593Smuzhiyunsource "drivers/reset/hisilicon/Kconfig"
253*4882a593Smuzhiyunsource "drivers/reset/tegra/Kconfig"
254*4882a593Smuzhiyun
255*4882a593Smuzhiyunendif
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