1*4882a593SmuzhiyunHisilicon System Reset Controller 2*4882a593Smuzhiyun====================================== 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunPlease also refer to reset.txt in this directory for common reset 5*4882a593Smuzhiyuncontroller binding usage. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunThe reset controller registers are part of the system-ctl block on 8*4882a593Smuzhiyunhi3660 and hi3670 SoCs. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunRequired properties: 11*4882a593Smuzhiyun- compatible: should be one of the following: 12*4882a593Smuzhiyun "hisilicon,hi3660-reset" for HI3660 13*4882a593Smuzhiyun "hisilicon,hi3670-reset", "hisilicon,hi3660-reset" for HI3670 14*4882a593Smuzhiyun- hisi,rst-syscon: phandle of the reset's syscon. 15*4882a593Smuzhiyun- #reset-cells : Specifies the number of cells needed to encode a 16*4882a593Smuzhiyun reset source. The type shall be a <u32> and the value shall be 2. 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun Cell #1 : offset of the reset assert control 19*4882a593Smuzhiyun register from the syscon register base 20*4882a593Smuzhiyun offset + 4: deassert control register 21*4882a593Smuzhiyun offset + 8: status control register 22*4882a593Smuzhiyun Cell #2 : bit position of the reset in the reset control register 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunExample: 25*4882a593Smuzhiyun iomcu: iomcu@ffd7e000 { 26*4882a593Smuzhiyun compatible = "hisilicon,hi3660-iomcu", "syscon"; 27*4882a593Smuzhiyun reg = <0x0 0xffd7e000 0x0 0x1000>; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun iomcu_rst: iomcu_rst_controller { 31*4882a593Smuzhiyun compatible = "hisilicon,hi3660-reset"; 32*4882a593Smuzhiyun hisi,rst-syscon = <&iomcu>; 33*4882a593Smuzhiyun #reset-cells = <2>; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593SmuzhiyunSpecifying reset lines connected to IP modules 37*4882a593Smuzhiyun============================================== 38*4882a593Smuzhiyunexample: 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun i2c0: i2c@..... { 41*4882a593Smuzhiyun ... 42*4882a593Smuzhiyun resets = <&iomcu_rst 0x20 3>; /* offset: 0x20; bit: 3 */ 43*4882a593Smuzhiyun ... 44*4882a593Smuzhiyun }; 45