1*4882a593Smuzhiyun* Device tree bindings for Texas Instruments keystone reset 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis node is intended to allow SoC reset in case of software reset 4*4882a593Smuzhiyunof selected watchdogs. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunThe Keystone SoCs can contain up to 4 watchdog timers to reset 7*4882a593SmuzhiyunSoC. Each watchdog timer event input is connected to the Reset Mux 8*4882a593Smuzhiyunblock. The Reset Mux block can be configured to cause reset or not. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunAdditionally soft or hard reset can be configured. 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunRequired properties: 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun- compatible: ti,keystone-reset 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun- ti,syscon-pll: phandle/offset pair. The phandle to syscon used to 17*4882a593Smuzhiyun access pll controller registers and the offset to use 18*4882a593Smuzhiyun reset control registers. 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun- ti,syscon-dev: phandle/offset pair. The phandle to syscon used to 21*4882a593Smuzhiyun access device state control registers and the offset 22*4882a593Smuzhiyun in order to use mux block registers for all watchdogs. 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunOptional properties: 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun- ti,soft-reset: Boolean option indicating soft reset. 27*4882a593Smuzhiyun By default hard reset is used. 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun- ti,wdt-list: WDT list that can cause SoC reset. It's not related 30*4882a593Smuzhiyun to WDT driver, it's just needed to enable a SoC related 31*4882a593Smuzhiyun reset that's triggered by one of WDTs. The list is 32*4882a593Smuzhiyun in format: <0>, <2>; It can be in random order and 33*4882a593Smuzhiyun begins from 0 to 3, as keystone can contain up to 4 SoC 34*4882a593Smuzhiyun reset watchdogs and can be in random order. 35*4882a593Smuzhiyun 36*4882a593SmuzhiyunExample 1: 37*4882a593SmuzhiyunSetup keystone reset so that in case software reset or 38*4882a593SmuzhiyunWDT0 is triggered it issues hard reset for SoC. 39*4882a593Smuzhiyun 40*4882a593Smuzhiyunpllctrl: pll-controller@2310000 { 41*4882a593Smuzhiyun compatible = "ti,keystone-pllctrl", "syscon"; 42*4882a593Smuzhiyun reg = <0x02310000 0x200>; 43*4882a593Smuzhiyun}; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyundevctrl: device-state-control@2620000 { 46*4882a593Smuzhiyun compatible = "ti,keystone-devctrl", "syscon"; 47*4882a593Smuzhiyun reg = <0x02620000 0x1000>; 48*4882a593Smuzhiyun}; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyunrstctrl: reset-controller { 51*4882a593Smuzhiyun compatible = "ti,keystone-reset"; 52*4882a593Smuzhiyun ti,syscon-pll = <&pllctrl 0xe4>; 53*4882a593Smuzhiyun ti,syscon-dev = <&devctrl 0x328>; 54*4882a593Smuzhiyun ti,wdt-list = <0>; 55*4882a593Smuzhiyun}; 56*4882a593Smuzhiyun 57*4882a593SmuzhiyunExample 2: 58*4882a593SmuzhiyunSetup keystone reset so that in case of software reset or 59*4882a593SmuzhiyunWDT0 or WDT2 is triggered it issues soft reset for SoC. 60*4882a593Smuzhiyun 61*4882a593Smuzhiyunrstctrl: reset-controller { 62*4882a593Smuzhiyun compatible = "ti,keystone-reset"; 63*4882a593Smuzhiyun ti,syscon-pll = <&pllctrl 0xe4>; 64*4882a593Smuzhiyun ti,syscon-dev = <&devctrl 0x328>; 65*4882a593Smuzhiyun ti,wdt-list = <0>, <2>; 66*4882a593Smuzhiyun ti,soft-reset; 67*4882a593Smuzhiyun}; 68