1*4882a593Smuzhiyunmenu "Reset Controller Support" 2*4882a593Smuzhiyun 3*4882a593Smuzhiyunconfig DM_RESET 4*4882a593Smuzhiyun bool "Enable reset controllers using Driver Model" 5*4882a593Smuzhiyun depends on DM && OF_CONTROL 6*4882a593Smuzhiyun help 7*4882a593Smuzhiyun Enable support for the reset controller driver class. Many hardware 8*4882a593Smuzhiyun modules are equipped with a reset signal, typically driven by some 9*4882a593Smuzhiyun reset controller hardware module within the chip. In U-Boot, reset 10*4882a593Smuzhiyun controller drivers allow control over these reset signals. In some 11*4882a593Smuzhiyun cases this API is applicable to chips outside the CPU as well, 12*4882a593Smuzhiyun although driving such reset isgnals using GPIOs may be more 13*4882a593Smuzhiyun appropriate in this case. 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunconfig SPL_DM_RESET 16*4882a593Smuzhiyun bool "Enable reset controllers using Driver Model in SPL" 17*4882a593Smuzhiyun depends on SPL_DM && OF_CONTROL 18*4882a593Smuzhiyun help 19*4882a593Smuzhiyun Enable support for the reset controller driver class. Many hardware 20*4882a593Smuzhiyun modules are equipped with a reset signal, typically driven by some 21*4882a593Smuzhiyun reset controller hardware module within the chip. In U-Boot, reset 22*4882a593Smuzhiyun controller drivers allow control over these reset signals. In some 23*4882a593Smuzhiyun cases this API is applicable to chips outside the CPU as well, 24*4882a593Smuzhiyun although driving such reset isgnals using GPIOs may be more 25*4882a593Smuzhiyun appropriate in this case. 26*4882a593Smuzhiyun 27*4882a593Smuzhiyunconfig SANDBOX_RESET 28*4882a593Smuzhiyun bool "Enable the sandbox reset test driver" 29*4882a593Smuzhiyun depends on DM_MAILBOX && SANDBOX 30*4882a593Smuzhiyun help 31*4882a593Smuzhiyun Enable support for a test reset controller implementation, which 32*4882a593Smuzhiyun simply accepts requests to reset various HW modules without actually 33*4882a593Smuzhiyun doing anything beyond a little error checking. 34*4882a593Smuzhiyun 35*4882a593Smuzhiyunconfig STI_RESET 36*4882a593Smuzhiyun bool "Enable the STi reset" 37*4882a593Smuzhiyun depends on ARCH_STI 38*4882a593Smuzhiyun help 39*4882a593Smuzhiyun Support for reset controllers on STMicroelectronics STiH407 family SoCs. 40*4882a593Smuzhiyun Say Y if you want to control reset signals provided by system config 41*4882a593Smuzhiyun block. 42*4882a593Smuzhiyun 43*4882a593Smuzhiyunconfig TEGRA_CAR_RESET 44*4882a593Smuzhiyun bool "Enable Tegra CAR-based reset driver" 45*4882a593Smuzhiyun depends on TEGRA_CAR 46*4882a593Smuzhiyun help 47*4882a593Smuzhiyun Enable support for manipulating Tegra's on-SoC reset signals via 48*4882a593Smuzhiyun direct register access to the Tegra CAR (Clock And Reset controller). 49*4882a593Smuzhiyun 50*4882a593Smuzhiyunconfig TEGRA186_RESET 51*4882a593Smuzhiyun bool "Enable Tegra186 BPMP-based reset driver" 52*4882a593Smuzhiyun depends on TEGRA186_BPMP 53*4882a593Smuzhiyun help 54*4882a593Smuzhiyun Enable support for manipulating Tegra's on-SoC reset signals via IPC 55*4882a593Smuzhiyun requests to the BPMP (Boot and Power Management Processor). 56*4882a593Smuzhiyun 57*4882a593Smuzhiyunconfig RESET_BCM6345 58*4882a593Smuzhiyun bool "Reset controller driver for BCM6345" 59*4882a593Smuzhiyun depends on DM_RESET && ARCH_BMIPS 60*4882a593Smuzhiyun help 61*4882a593Smuzhiyun Support reset controller on BCM6345. 62*4882a593Smuzhiyun 63*4882a593Smuzhiyunconfig RESET_UNIPHIER 64*4882a593Smuzhiyun bool "Reset controller driver for UniPhier SoCs" 65*4882a593Smuzhiyun depends on ARCH_UNIPHIER 66*4882a593Smuzhiyun default y 67*4882a593Smuzhiyun help 68*4882a593Smuzhiyun Support for reset controllers on UniPhier SoCs. 69*4882a593Smuzhiyun Say Y if you want to control reset signals provided by System Control 70*4882a593Smuzhiyun block, Media I/O block, Peripheral Block. 71*4882a593Smuzhiyun 72*4882a593Smuzhiyunconfig AST2500_RESET 73*4882a593Smuzhiyun bool "Reset controller driver for AST2500 SoCs" 74*4882a593Smuzhiyun depends on DM_RESET && WDT_ASPEED 75*4882a593Smuzhiyun default y if ASPEED_AST2500 76*4882a593Smuzhiyun help 77*4882a593Smuzhiyun Support for reset controller on AST2500 SoC. This controller uses 78*4882a593Smuzhiyun watchdog to reset different peripherals and thus only supports 79*4882a593Smuzhiyun resets that are supported by watchdog. The main limitation though 80*4882a593Smuzhiyun is that some reset signals, like I2C or MISC reset multiple devices. 81*4882a593Smuzhiyun 82*4882a593Smuzhiyunconfig RESET_ROCKCHIP 83*4882a593Smuzhiyun bool "Reset controller driver for Rockchip SoCs" 84*4882a593Smuzhiyun depends on DM_RESET && CLK 85*4882a593Smuzhiyun default y 86*4882a593Smuzhiyun help 87*4882a593Smuzhiyun Support for reset controller on rockchip SoC. The main limitation though 88*4882a593Smuzhiyun is that some reset signals, like I2C or MISC reset multiple devices. 89*4882a593Smuzhiyun 90*4882a593Smuzhiyunconfig SPL_RESET_ROCKCHIP 91*4882a593Smuzhiyun bool "Reset controller driver for Rockchip SoCs in SPL" 92*4882a593Smuzhiyun depends on SPL_DM_RESET && SPL_CLK 93*4882a593Smuzhiyun help 94*4882a593Smuzhiyun Support for reset controller on rockchip SoC. The main limitation though 95*4882a593Smuzhiyun is that some reset signals, like I2C or MISC reset multiple devices. 96*4882a593Smuzhiyun 97*4882a593Smuzhiyunconfig RESET_SCMI 98*4882a593Smuzhiyun bool "Enable SCMI reset domain driver" 99*4882a593Smuzhiyun select SCMI_FIRMWARE 100*4882a593Smuzhiyun help 101*4882a593Smuzhiyun Enable this option if you want to support reset controller 102*4882a593Smuzhiyun devices exposed by a SCMI agent based on SCMI reset domain 103*4882a593Smuzhiyun protocol communication with a SCMI server. 104*4882a593Smuzhiyunendmenu 105