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Searched refs:pll_rate (Results 1 – 25 of 33) sorted by relevance

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/OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/disp/mdp4/
H A Dmdp4_lvds_pll.c25 struct pll_rate { struct
34 static const struct pll_rate freqtbl[] = { argument
48 static const struct pll_rate *find_rate(unsigned long rate) in find_rate()
61 const struct pll_rate *pll_rate = find_rate(lvds_pll->pixclk); in mpd4_lvds_pll_enable() local
64 DBG("pixclk=%lu (%lu)", lvds_pll->pixclk, pll_rate->rate); in mpd4_lvds_pll_enable()
66 if (WARN_ON(!pll_rate)) in mpd4_lvds_pll_enable()
71 for (i = 0; pll_rate->conf[i].reg; i++) in mpd4_lvds_pll_enable()
72 mdp4_write(mdp4_kms, pll_rate->conf[i].reg, pll_rate->conf[i].val); in mpd4_lvds_pll_enable()
104 const struct pll_rate *pll_rate = find_rate(rate); in mpd4_lvds_pll_round_rate() local
105 return pll_rate->rate; in mpd4_lvds_pll_round_rate()
/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/
H A Dclock.c26 static unsigned pll_rate[CLOCK_ID_COUNT]; variable
275 div = clk_get_divider(8, pll_rate[clkid], rate); in clock_set_pllout()
314 unsigned parent_rate = pll_rate[parent]; in clock_get_periph_rate()
452 divider = find_best_divider(divider_bits, pll_rate[parent], in clock_adjust_periph_pll_div()
690 pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL); in clock_init()
691 pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY); in clock_init()
692 pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH); in clock_init()
693 pll_rate[CLOCK_ID_USB] = clock_get_rate(CLOCK_ID_USB); in clock_init()
694 pll_rate[CLOCK_ID_DISPLAY] = clock_get_rate(CLOCK_ID_DISPLAY); in clock_init()
695 pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU); in clock_init()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/hdmi/
H A Dhdmi_pll_8960.c30 struct pll_rate { struct
40 static const struct pll_rate freqtbl[] = { argument
357 static const struct pll_rate *find_rate(unsigned long rate) in find_rate()
379 const struct pll_rate *pll_rate = find_rate(rate); in hdmi_pll_round_rate() local
381 return pll_rate->rate; in hdmi_pll_round_rate()
388 const struct pll_rate *pll_rate = find_rate(rate); in hdmi_pll_set_rate() local
393 for (i = 0; i < pll_rate->num_reg; i++) in hdmi_pll_set_rate()
394 pll_write(pll, pll_rate->conf[i].reg, pll_rate->conf[i].val); in hdmi_pll_set_rate()
/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rv1108.c146 ulong pll_rate; in rv1108_mac_set_clk() local
150 pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_mac_set_clk()
152 pll_rate = rkclk_pll_get_rate(cru, CLK_ARM); in rv1108_mac_set_clk()
158 div = DIV_ROUND_UP(pll_rate, rate) - 1; in rv1108_mac_set_clk()
165 return DIV_TO_RATE(pll_rate, div); in rv1108_mac_set_clk()
171 u32 pll_rate; in rv1108_sfc_set_clk() local
175 pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_sfc_set_clk()
177 pll_rate = rkclk_pll_get_rate(cru, CLK_DDR); in rv1108_sfc_set_clk()
179 div = DIV_ROUND_UP(pll_rate, rate) - 1; in rv1108_sfc_set_clk()
186 return DIV_TO_RATE(pll_rate, div); in rv1108_sfc_set_clk()
[all …]
H A Dclk_rk3308.c265 ulong pll_rate; in rk3308_mac_set_clk() local
269 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_mac_set_clk()
272 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL1], in rk3308_mac_set_clk()
275 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL], in rk3308_mac_set_clk()
282 div = DIV_ROUND_UP(pll_rate, hz) - 1; in rk3308_mac_set_clk()
287 return DIV_TO_RATE(pll_rate, div); in rk3308_mac_set_clk()
564 ulong pll_rate, now, best_rate = 0; in rk3308_vop_set_clk() local
570 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk()
573 pll_rate = priv->vpll0_hz; in rk3308_vop_set_clk()
576 pll_rate = priv->vpll1_hz; in rk3308_vop_set_clk()
[all …]
H A Dclk_rk3328.c261 ulong pll_rate; in rk3328_gmac2io_set_clk() local
265 pll_rate = priv->gpll_hz; in rk3328_gmac2io_set_clk()
267 pll_rate = priv->cpll_hz; in rk3328_gmac2io_set_clk()
269 div = DIV_ROUND_UP(pll_rate, rate) - 1; in rk3328_gmac2io_set_clk()
276 return DIV_TO_RATE(pll_rate, div); in rk3328_gmac2io_set_clk()
285 ulong pll_rate; in rk3328_gmac2phy_src_set_clk() local
289 pll_rate = GPLL_HZ; in rk3328_gmac2phy_src_set_clk()
291 pll_rate = CPLL_HZ; in rk3328_gmac2phy_src_set_clk()
293 div = DIV_ROUND_UP(pll_rate, rate) - 1; in rk3328_gmac2phy_src_set_clk()
300 return DIV_TO_RATE(pll_rate, div); in rk3328_gmac2phy_src_set_clk()
H A Dclk_rk3368.c296 u32 pll_rate; in rk3368_mmc_get_clk() local
315 pll_rate = rkclk_pll_get_rate(cru, GPLL); in rk3368_mmc_get_clk()
318 pll_rate = OSC_HZ; in rk3368_mmc_get_clk()
321 pll_rate = rkclk_pll_get_rate(cru, CPLL); in rk3368_mmc_get_clk()
328 rate = DIV_TO_RATE(pll_rate, div); in rk3368_mmc_get_clk()
461 ulong pll_rate; in rk3368_gmac_set_clk() local
466 pll_rate = GPLL_HZ; in rk3368_gmac_set_clk()
469 pll_rate = CPLL_HZ; in rk3368_gmac_set_clk()
474 div = DIV_ROUND_UP(pll_rate, set_rate) - 1; in rk3368_gmac_set_clk()
481 return DIV_TO_RATE(pll_rate, div); in rk3368_gmac_set_clk()
H A Dclk_rk3588.c1112 ulong pll_rate, now, best_rate = 0; in rk3588_dclk_vop_set_clk() local
1157 pll_rate = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL], in rk3588_dclk_vop_set_clk()
1159 if (pll_rate >= RK3588_VOP_PLL_LIMIT_FREQ && pll_rate % rate == 0) { in rk3588_dclk_vop_set_clk()
1160 div = DIV_ROUND_UP(pll_rate, rate); in rk3588_dclk_vop_set_clk()
1178 pll_rate = priv->gpll_hz; in rk3588_dclk_vop_set_clk()
1181 pll_rate = priv->cpll_hz; in rk3588_dclk_vop_set_clk()
1184 pll_rate = priv->aupll_hz; in rk3588_dclk_vop_set_clk()
1187 pll_rate = 0; in rk3588_dclk_vop_set_clk()
1194 div = DIV_ROUND_UP(pll_rate, rate); in rk3588_dclk_vop_set_clk()
1197 now = pll_rate / div; in rk3588_dclk_vop_set_clk()
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H A Dclk_rk3288.c449 ulong pll_rate; in rockchip_mac_set_clk() local
454 pll_rate = GPLL_HZ; in rockchip_mac_set_clk()
457 pll_rate = CPLL_HZ; in rockchip_mac_set_clk()
459 pll_rate = NPLL_HZ; in rockchip_mac_set_clk()
461 div = DIV_ROUND_UP(pll_rate, freq) - 1; in rockchip_mac_set_clk()
468 return DIV_TO_RATE(pll_rate, div); in rockchip_mac_set_clk()
H A Dclk_rk1808.c599 ulong pll_rate; in rk1808_mac_set_clk() local
603 pll_rate = rockchip_pll_get_rate(&rk1808_pll_clks[NPLL], in rk1808_mac_set_clk()
606 pll_rate = rockchip_pll_get_rate(&rk1808_pll_clks[PPLL], in rk1808_mac_set_clk()
609 pll_rate = rockchip_pll_get_rate(&rk1808_pll_clks[CPLL], in rk1808_mac_set_clk()
616 div = DIV_ROUND_UP(pll_rate, hz) - 1; in rk1808_mac_set_clk()
621 return DIV_TO_RATE(pll_rate, div); in rk1808_mac_set_clk()
/OK3568_Linux_fs/kernel/arch/mips/ralink/
H A Dmt7620.c451 mt7620_get_cpu_rate(unsigned long pll_rate) in mt7620_get_cpu_rate() argument
463 return mt7620_calc_rate(pll_rate, mul, div); in mt7620_get_cpu_rate()
475 mt7620_get_dram_rate(unsigned long pll_rate) in mt7620_get_dram_rate() argument
478 return pll_rate / 4; in mt7620_get_dram_rate()
480 return pll_rate / 3; in mt7620_get_dram_rate()
509 unsigned long pll_rate; in ralink_clk_init() local
535 pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate); in ralink_clk_init()
537 cpu_rate = mt7620_get_cpu_rate(pll_rate); in ralink_clk_init()
538 dram_rate = mt7620_get_dram_rate(pll_rate); in ralink_clk_init()
546 RINT(pll_rate), RFRAC(pll_rate)); in ralink_clk_init()
/OK3568_Linux_fs/u-boot/drivers/clk/
H A Dclk_zynqmp.c424 ulong pll_rate, in zynqmp_clk_calc_peripheral_two_divs() argument
434 DIV_ROUND_CLOSEST(pll_rate, d0), d1); in zynqmp_clk_calc_peripheral_two_divs()
455 ulong pll_rate, new_rate; in zynqmp_clk_set_peripheral_rate() local
468 pll_rate = zynqmp_clk_get_pll_rate(priv, pll); in zynqmp_clk_set_peripheral_rate()
469 if (IS_ERR_VALUE(pll_rate)) in zynqmp_clk_set_peripheral_rate()
470 return pll_rate; in zynqmp_clk_set_peripheral_rate()
475 new_rate = zynqmp_clk_calc_peripheral_two_divs(rate, pll_rate, in zynqmp_clk_set_peripheral_rate()
479 div0 = DIV_ROUND_CLOSEST(pll_rate, rate); in zynqmp_clk_set_peripheral_rate()
H A Dclk_zynq.c289 ulong pll_rate, in zynq_clk_calc_peripheral_two_divs() argument
299 DIV_ROUND_CLOSEST(pll_rate, d0), d1); in zynq_clk_calc_peripheral_two_divs()
320 ulong pll_rate, new_rate; in zynq_clk_set_peripheral_rate() local
327 pll_rate = zynq_clk_get_pll_rate(priv, pll); in zynq_clk_set_peripheral_rate()
331 new_rate = zynq_clk_calc_peripheral_two_divs(rate, pll_rate, in zynq_clk_set_peripheral_rate()
335 div0 = DIV_ROUND_CLOSEST(pll_rate, rate); in zynq_clk_set_peripheral_rate()
/OK3568_Linux_fs/kernel/sound/soc/samsung/
H A Dsnow.c30 static const unsigned int pll_rate[] = { in snow_card_hw_params() local
79 for (i = 0; i < ARRAY_SIZE(pll_rate); i++) { in snow_card_hw_params()
80 if ((pll_rate[i] - rclk * psr) <= 2) { in snow_card_hw_params()
81 freq = pll_rate[i]; in snow_card_hw_params()
/OK3568_Linux_fs/kernel/sound/soc/tegra/
H A Dtegra_asoc_utils.c93 const int pll_rate = 73728000; in tegra_asoc_utils_set_ac97_rate() local
103 err = clk_set_rate(data->clk_pll_a, pll_rate); in tegra_asoc_utils_set_ac97_rate()
123 data->set_baseclock = pll_rate; in tegra_asoc_utils_set_ac97_rate()
/OK3568_Linux_fs/kernel/sound/soc/ti/
H A Dj721e-evm.c561 unsigned int min_rate, max_rate, pll_rate; in j721e_calculate_rate_range() local
591 pll_rate = priv->pll_rates[J721E_CLK_PARENT_44100]; in j721e_calculate_rate_range()
593 pll_rate = priv->pll_rates[J721E_CLK_PARENT_48000]; in j721e_calculate_rate_range()
595 min_rate = pll_rate / J721E_MAX_CLK_HSDIV; in j721e_calculate_rate_range()
599 pll_rate = priv->pll_rates[J721E_CLK_PARENT_48000]; in j721e_calculate_rate_range()
601 pll_rate = priv->pll_rates[J721E_CLK_PARENT_44100]; in j721e_calculate_rate_range()
603 if (pll_rate > PCM1368A_MAX_SYSCLK) in j721e_calculate_rate_range()
604 pll_rate = PCM1368A_MAX_SYSCLK; in j721e_calculate_rate_range()
606 max_rate = pll_rate / ratios_for_pcm3168a[0]; in j721e_calculate_rate_range()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/mediatek/
H A Dmtk_dpi.c420 unsigned long pll_rate; in mtk_dpi_set_display_mode() local
426 pll_rate = vm.pixelclock * factor; in mtk_dpi_set_display_mode()
429 pll_rate, vm.pixelclock); in mtk_dpi_set_display_mode()
431 clk_set_rate(dpi->tvd_clk, pll_rate); in mtk_dpi_set_display_mode()
432 pll_rate = clk_get_rate(dpi->tvd_clk); in mtk_dpi_set_display_mode()
434 vm.pixelclock = pll_rate / factor; in mtk_dpi_set_display_mode()
439 pll_rate, vm.pixelclock); in mtk_dpi_set_display_mode()
/OK3568_Linux_fs/kernel/drivers/mfd/
H A Ddb8500-prcmu.c1396 static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate, in pll_rate() function
1452 rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch); in clock_rate()
1454 rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch); in clock_rate()
1456 rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch); in clock_rate()
1484 rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX); in armss_rate()
1496 rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV); in armss_rate()
1523 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), in dsiclk_rate()
1549 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW); in prcmu_clock_rate()
1551 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW); in prcmu_clock_rate()
1555 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW); in prcmu_clock_rate()
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/OK3568_Linux_fs/kernel/sound/soc/codecs/
H A Dpcm512x.c748 unsigned long pll_rate) in pcm512x_find_pll_coeff() argument
759 common = gcd(pll_rate, pllin_rate); in pcm512x_find_pll_coeff()
761 pll_rate, pllin_rate, common); in pcm512x_find_pll_coeff()
762 num = pll_rate / common; in pcm512x_find_pll_coeff()
786 pcm512x->real_pll = pll_rate; in pcm512x_find_pll_coeff()
816 pcm512x->real_pll = pll_rate; in pcm512x_find_pll_coeff()
835 K = DIV_ROUND_CLOSEST_ULL(10000ULL * pll_rate * P, pllin_rate); in pcm512x_find_pll_coeff()
892 unsigned long pll_rate; in pcm512x_set_dividers() local
945 pll_rate = 4 * sck_rate; in pcm512x_set_dividers()
947 ret = pcm512x_find_pll_coeff(dai, pllin_rate, pll_rate); in pcm512x_set_dividers()
H A Dadau17x1.c429 unsigned int pll_rate; in adau17x1_auto_pll() local
439 pll_rate = 48000 * 1024; in adau17x1_auto_pll()
448 pll_rate = 44100 * 1024; in adau17x1_auto_pll()
455 clk_get_rate(adau->mclk), pll_rate); in adau17x1_auto_pll()
/OK3568_Linux_fs/kernel/drivers/clk/spear/
H A Dclk-vco-pll.c70 unsigned long prate, int index, unsigned long *pll_rate) in pll_calc_rate() argument
78 if (pll_rate) in pll_calc_rate()
79 *pll_rate = (rate / (1 << rtbl[index].p)) * 10000; in pll_calc_rate()
/OK3568_Linux_fs/kernel/arch/arm/mach-omap1/
H A Dopp.h18 unsigned long pll_rate; member
/OK3568_Linux_fs/kernel/drivers/phy/mediatek/
H A Dphy-mtk-hdmi-mt8173.c147 hdmi_phy->pll_rate = rate; in mtk_hdmi_pll_round_rate()
247 return hdmi_phy->pll_rate; in mtk_hdmi_pll_recalc_rate()
H A Dphy-mtk-hdmi.h36 unsigned long pll_rate; member
/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-cdce925.c419 long pll_rate = clk_round_rate(pll, target_rate); in cdce925_clk_best_parent_rate() local
423 if (pll_rate <= 0) in cdce925_clk_best_parent_rate()
425 actual_rate = pll_rate / pdiv_now; in cdce925_clk_best_parent_rate()

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