Lines Matching refs:pll_rate
1112 ulong pll_rate, now, best_rate = 0; in rk3588_dclk_vop_set_clk() local
1157 pll_rate = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL], in rk3588_dclk_vop_set_clk()
1159 if (pll_rate >= RK3588_VOP_PLL_LIMIT_FREQ && pll_rate % rate == 0) { in rk3588_dclk_vop_set_clk()
1160 div = DIV_ROUND_UP(pll_rate, rate); in rk3588_dclk_vop_set_clk()
1178 pll_rate = priv->gpll_hz; in rk3588_dclk_vop_set_clk()
1181 pll_rate = priv->cpll_hz; in rk3588_dclk_vop_set_clk()
1184 pll_rate = priv->aupll_hz; in rk3588_dclk_vop_set_clk()
1187 pll_rate = 0; in rk3588_dclk_vop_set_clk()
1194 div = DIV_ROUND_UP(pll_rate, rate); in rk3588_dclk_vop_set_clk()
1197 now = pll_rate / div; in rk3588_dclk_vop_set_clk()
1204 pll_rate, best_rate, best_div, best_sel); in rk3588_dclk_vop_set_clk()