1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2018 MediaTek Inc. 4*4882a593Smuzhiyun * Author: Chunhui Dai <chunhui.dai@mediatek.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _MTK_HDMI_PHY_H 8*4882a593Smuzhiyun #define _MTK_HDMI_PHY_H 9*4882a593Smuzhiyun #include <linux/clk.h> 10*4882a593Smuzhiyun #include <linux/clk-provider.h> 11*4882a593Smuzhiyun #include <linux/delay.h> 12*4882a593Smuzhiyun #include <linux/io.h> 13*4882a593Smuzhiyun #include <linux/mfd/syscon.h> 14*4882a593Smuzhiyun #include <linux/module.h> 15*4882a593Smuzhiyun #include <linux/of_device.h> 16*4882a593Smuzhiyun #include <linux/phy/phy.h> 17*4882a593Smuzhiyun #include <linux/platform_device.h> 18*4882a593Smuzhiyun #include <linux/types.h> 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun struct mtk_hdmi_phy; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun struct mtk_hdmi_phy_conf { 23*4882a593Smuzhiyun unsigned long flags; 24*4882a593Smuzhiyun bool pll_default_off; 25*4882a593Smuzhiyun const struct clk_ops *hdmi_phy_clk_ops; 26*4882a593Smuzhiyun void (*hdmi_phy_enable_tmds)(struct mtk_hdmi_phy *hdmi_phy); 27*4882a593Smuzhiyun void (*hdmi_phy_disable_tmds)(struct mtk_hdmi_phy *hdmi_phy); 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun struct mtk_hdmi_phy { 31*4882a593Smuzhiyun void __iomem *regs; 32*4882a593Smuzhiyun struct device *dev; 33*4882a593Smuzhiyun struct mtk_hdmi_phy_conf *conf; 34*4882a593Smuzhiyun struct clk *pll; 35*4882a593Smuzhiyun struct clk_hw pll_hw; 36*4882a593Smuzhiyun unsigned long pll_rate; 37*4882a593Smuzhiyun unsigned char drv_imp_clk; 38*4882a593Smuzhiyun unsigned char drv_imp_d2; 39*4882a593Smuzhiyun unsigned char drv_imp_d1; 40*4882a593Smuzhiyun unsigned char drv_imp_d0; 41*4882a593Smuzhiyun unsigned int ibias; 42*4882a593Smuzhiyun unsigned int ibias_up; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset, 46*4882a593Smuzhiyun u32 bits); 47*4882a593Smuzhiyun void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset, 48*4882a593Smuzhiyun u32 bits); 49*4882a593Smuzhiyun void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset, 50*4882a593Smuzhiyun u32 val, u32 mask); 51*4882a593Smuzhiyun struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw); 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf; 54*4882a593Smuzhiyun extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #endif /* _MTK_HDMI_PHY_H */ 57