146 	ulong pll_rate;  in rv1108_mac_set_clk()  local
150 		pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);  in rv1108_mac_set_clk()
152 		pll_rate = rkclk_pll_get_rate(cru, CLK_ARM);  in rv1108_mac_set_clk()
158 	div = DIV_ROUND_UP(pll_rate, rate) - 1;  in rv1108_mac_set_clk()
165 	return DIV_TO_RATE(pll_rate, div);  in rv1108_mac_set_clk()
171 	u32 pll_rate;  in rv1108_sfc_set_clk()  local
175 		pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);  in rv1108_sfc_set_clk()
177 		pll_rate = rkclk_pll_get_rate(cru, CLK_DDR);  in rv1108_sfc_set_clk()
179 	div = DIV_ROUND_UP(pll_rate, rate) - 1;  in rv1108_sfc_set_clk()
186 	return DIV_TO_RATE(pll_rate, div);  in rv1108_sfc_set_clk()
532 	u32 pll_rate;  in rv1108_mmc_set_clk()  local
540 		pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);  in rv1108_mmc_set_clk()
545 		pll_rate = OSC_HZ;  in rv1108_mmc_set_clk()
548 	div = DIV_ROUND_UP(pll_rate / 2, rate);  in rv1108_mmc_set_clk()
554 	return DIV_TO_RATE(pll_rate, div);  in rv1108_mmc_set_clk()