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Searched refs:clrsetbits_le32 (Results 1 – 25 of 198) sorted by relevance

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/OK3568_Linux_fs/u-boot/arch/arm/mach-omap2/omap3/
H A Dclock.c136 clrsetbits_le32(&prcm_base->clken_pll, in dpll3_init_34xx()
147 clrsetbits_le32(&prcm_base->clksel1_emu, in dpll3_init_34xx()
149 clrsetbits_le32(&prcm_base->clksel1_emu, in dpll3_init_34xx()
153 clrsetbits_le32(&prcm_base->clksel1_pll, in dpll3_init_34xx()
157 clrsetbits_le32(&prcm_base->clksel1_pll, in dpll3_init_34xx()
161 clrsetbits_le32(&prcm_base->clksel1_pll, in dpll3_init_34xx()
168 clrsetbits_le32(&prcm_base->clksel_core, in dpll3_init_34xx()
171 clrsetbits_le32(&prcm_base->clksel_core, in dpll3_init_34xx()
174 clrsetbits_le32(&prcm_base->clksel_core, in dpll3_init_34xx()
177 clrsetbits_le32(&prcm_base->clksel_core, in dpll3_init_34xx()
[all …]
H A Dam35x_musb.c19 clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset, in am35x_musb_reset()
21 clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset, in am35x_musb_reset()
33 clrsetbits_le32(&am35x_scm_general_regs->devconf2, in am35x_musb_phy_power()
50 clrsetbits_le32(&am35x_scm_general_regs->devconf2, in am35x_musb_phy_power()
58 clrsetbits_le32(&am35x_scm_general_regs->lvl_intr_clr, in am35x_musb_clear_irq()
/OK3568_Linux_fs/u-boot/drivers/ram/rockchip/
H A Dsdram_rk3399.c164 clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->cap_info.col)); in set_memory_map()
165 clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24), in set_memory_map()
169 clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16), in set_memory_map()
173 clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->cap_info.col)); in set_memory_map()
176 clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24), in set_memory_map()
189 clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24); in set_memory_map()
297 clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8); in phy_io_config()
299 clrsetbits_le32(&denali_phy[914], 0xfff, reg_value); in phy_io_config()
301 clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16); in phy_io_config()
303 clrsetbits_le32(&denali_phy[915], 0xfff, reg_value); in phy_io_config()
[all …]
H A Dsdram_phy_px30.c72 clrsetbits_le32(PHY_REG(phy_base, 0x12), 0x1f << 3, cmd_drv << 3); in sdram_phy_set_ds_odt()
99 clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 0xf << 4); in phy_dram_set_bw()
103 clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 3 << 4); in phy_dram_set_bw()
107 clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 1 << 4); in phy_dram_set_bw()
131 clrsetbits_le32(PHY_REG(phy_base, 0x29), 0x3, 0); in phy_data_training()
132 clrsetbits_le32(PHY_REG(phy_base, 0x39), 0x3, 0); in phy_data_training()
133 clrsetbits_le32(PHY_REG(phy_base, 0x49), 0x3, 0); in phy_data_training()
134 clrsetbits_le32(PHY_REG(phy_base, 0x59), 0x3, 0); in phy_data_training()
137 clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs)); in phy_data_training()
139 clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs) | 1); in phy_data_training()
[all …]
H A Dsdram_rv1126.c358 clrsetbits_le32(&dram->cru->pll[1].con2, in rkclk_set_dpll()
555 clrsetbits_le32(pctl_base + DDR_PCTL2_ADDRMAP0, 0x1f, 0x1f); in set_ctl_address_map()
591 clrsetbits_le32(PHY_REG(phy_base, 0x51), PHY_PBDIV_BIT9_MASK, in phy_pll_set()
593 clrsetbits_le32(PHY_REG(phy_base, 0x51), PHY_POSTDIV_EN_MASK, in phy_pll_set()
596 clrsetbits_le32(PHY_REG(phy_base, 0x52), in phy_pll_set()
598 clrsetbits_le32(PHY_REG(phy_base, 0x53), in phy_pll_set()
865 clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + in set_lp4_vref()
870 clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + in set_lp4_vref()
1037 clrsetbits_le32(PHY_REG(phy_base, 0x100), 0x1f, phy_ca_drv); in set_ds_odt()
1038 clrsetbits_le32(PHY_REG(phy_base, 0x101), 0x1f, phy_ca_drv); in set_ds_odt()
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/vf610twr/
H A Dvf610twr.c274 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, in clock_init()
276 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, in clock_init()
278 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, in clock_init()
283 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, in clock_init()
285 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, in clock_init()
288 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, in clock_init()
290 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, in clock_init()
292 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, in clock_init()
294 clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, in clock_init()
297 clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN, in clock_init()
[all …]
/OK3568_Linux_fs/u-boot/board/toradex/colibri_vf/
H A Dcolibri_vf.c390 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, in clock_init()
395 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, in clock_init()
397 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, in clock_init()
401 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, in clock_init()
403 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, in clock_init()
406 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, in clock_init()
408 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, in clock_init()
410 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, in clock_init()
412 clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, in clock_init()
419 clrsetbits_le32(&anadig->pll3_ctrl, ANADIG_PLL3_CTRL_BYPASS | in clock_init()
[all …]
/OK3568_Linux_fs/u-boot/drivers/usb/host/
H A Dehci-tegra.c321 clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK, in init_phy_mux()
325 clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, in init_phy_mux()
331 clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC, in init_phy_mux()
340 clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK, in init_phy_mux()
370 clrsetbits_le32(&usbctlr->phy_vbus_sensors, b_sess_valid_mask, in init_utmi_usb_controller()
379 clrsetbits_le32(&usbctlr->usb1_legacy_ctrl, in init_utmi_usb_controller()
394 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, in init_utmi_usb_controller()
397 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, in init_utmi_usb_controller()
404 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, in init_utmi_usb_controller()
407 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, in init_utmi_usb_controller()
[all …]
/OK3568_Linux_fs/u-boot/board/samsung/odroid/
H A Dodroid.c113 clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set); in board_clock_init()
123 clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set); in board_clock_init()
132 clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set); in board_clock_init()
156 clrsetbits_le32(&clk->div_cpu0, clr, set); in board_clock_init()
171 clrsetbits_le32(&clk->div_cpu1, clr, set); in board_clock_init()
197 clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set); in board_clock_init()
206 clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set); in board_clock_init()
217 clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set); in board_clock_init()
241 clrsetbits_le32(&clk->div_dmc0, clr, set); in board_clock_init()
264 clrsetbits_le32(&clk->div_dmc1, clr, set); in board_clock_init()
[all …]
/OK3568_Linux_fs/u-boot/board/phytec/pcm052/
H A Dpcm052.c468 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, in clock_init()
470 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, in clock_init()
472 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, in clock_init()
477 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, in clock_init()
479 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, in clock_init()
482 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, in clock_init()
484 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, in clock_init()
486 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, in clock_init()
488 clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, in clock_init()
491 clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN, in clock_init()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/cpu/arm926ejs/mxs/
H A Dspl_power_init.c130 clrsetbits_le32(&power_regs->hw_power_vdddctrl, in mxs_power_set_linreg()
135 clrsetbits_le32(&power_regs->hw_power_vddactrl, in mxs_power_set_linreg()
140 clrsetbits_le32(&power_regs->hw_power_vddioctrl, in mxs_power_set_linreg()
192 clrsetbits_le32(&power_regs->hw_power_5vctrl, in mxs_is_batt_good()
198 clrsetbits_le32(&power_regs->hw_power_charge, in mxs_is_batt_good()
244 clrsetbits_le32(&power_regs->hw_power_5vctrl, in mxs_power_setup_5v_detect()
263 clrsetbits_le32(&power_regs->hw_power_misc, in mxs_power_switch_dcdc_clocksource()
300 clrsetbits_le32(&power_regs->hw_power_dclimits, in mxs_src_power_init()
308 clrsetbits_le32(&power_regs->hw_power_loopctrl, in mxs_src_power_init()
313 clrsetbits_le32(&power_regs->hw_power_minpwr, in mxs_src_power_init()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-omap2/am33xx/
H A Dclock_am33xx.c151 clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, in setup_clocks_for_console()
155 clrsetbits_le32(&cmper->l4hsclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, in setup_clocks_for_console()
159 clrsetbits_le32(&cmwkup->wkup_uart0ctrl, in setup_clocks_for_console()
163 clrsetbits_le32(&cmper->uart1clkctrl, in setup_clocks_for_console()
167 clrsetbits_le32(&cmper->uart2clkctrl, in setup_clocks_for_console()
171 clrsetbits_le32(&cmper->uart3clkctrl, in setup_clocks_for_console()
175 clrsetbits_le32(&cmper->uart4clkctrl, in setup_clocks_for_console()
179 clrsetbits_le32(&cmper->uart5clkctrl, in setup_clocks_for_console()
H A Dclock.c36 clrsetbits_le32(dpll_regs->cm_clkmode_dpll, in do_lock_dpll()
53 clrsetbits_le32(dpll_regs->cm_clkmode_dpll, in do_bypass_dpll()
140 clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK, in enable_clock_module()
166 clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK, in disable_clock_module()
176 clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK, in enable_clock_domain()
183 clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK, in disable_clock_domain()
/OK3568_Linux_fs/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun8i_a83t.c218 clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x3 << 24); in mctl_data_train_cfg()
220 clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x1 << 24); in mctl_data_train_cfg()
279 clrsetbits_le32(&mctl_ctl->pgcr1, 0x1 << 24, 0x1 << 26); in mctl_channel_init()
283 clrsetbits_le32(MX_UPD2, 0xfff << 16, 0x50 << 16); in mctl_channel_init()
295 clrsetbits_le32(DATX0IOCR(i), (0x3 << 24) | (0x3 << 16), in mctl_channel_init()
297 clrsetbits_le32(DATX1IOCR(i), (0x3 << 24) | (0x3 << 16), in mctl_channel_init()
299 clrsetbits_le32(DATX2IOCR(i), (0x3 << 24) | (0x3 << 16), in mctl_channel_init()
301 clrsetbits_le32(DATX3IOCR(i), (0x3 << 24) | (0x3 << 16), in mctl_channel_init()
306 clrsetbits_le32(CAIOCR(i), 0x3 << 26 | 0x3 << 16, 0x2 << 26); in mctl_channel_init()
325 clrsetbits_le32(&mctl_ctl->dxccr, (0x1 << 27) | (0x3<<6) , in mctl_channel_init()
[all …]
H A Ddram_sunxi_dw.c284 clrsetbits_le32(&mctl_ctl->zqcr, 0xffff, in mctl_h3_zq_calibration_quirk()
386 clrsetbits_le32(&ccm->dram_clk_cfg, in mctl_sys_init()
394 clrsetbits_le32(&ccm->dram_clk_cfg, in mctl_sys_init()
438 clrsetbits_le32(&mctl_ctl->pgcr[1], 1 << 24, 1 << 26); in mctl_channel_init()
443 clrsetbits_le32(&mctl_ctl->upd2, 0xfff << 16, 0x50 << 16); in mctl_channel_init()
458 clrsetbits_le32(&mctl_ctl->dx[i].gcr, clearmask, setmask); in mctl_channel_init()
462 clrsetbits_le32(&mctl_ctl->aciocr, socid == SOCID_H5 ? (0x1 << 11) : 0, in mctl_channel_init()
473 clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8), in mctl_channel_init()
477 clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8), in mctl_channel_init()
484 clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8), in mctl_channel_init()
[all …]
H A Ddram_sun4i.c104 clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28), in mctl_set_drive()
106 clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3), in mctl_set_drive()
116 clrsetbits_le32(&dram->ccr, DRAM_CCR_INIT, DRAM_CCR_ITM_OFF); in mctl_itm_disable()
138 clrsetbits_le32(&dram->dllcr[0], 0x3f << 6, in mctl_enable_dll0()
140 clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET, DRAM_DLLCR_DISABLE); in mctl_enable_dll0()
146 clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_DISABLE, DRAM_DLLCR_NRESET); in mctl_enable_dll0()
172 clrsetbits_le32(&dram->dllcr[i], 0xf << 14, in mctl_enable_dllx()
174 clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET, in mctl_enable_dllx()
186 clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_DISABLE, in mctl_enable_dllx()
656 clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE); in dramc_init_helper()
/OK3568_Linux_fs/u-boot/arch/x86/cpu/ivybridge/
H A Dlpc.c267 clrsetbits_le32(RCB_REG(0x3314), ~0x1f, 0xf); in cpt_pm_init()
284 clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060); in cpt_pm_init()
288 clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001); in cpt_pm_init()
292 clrsetbits_le32(RCB_REG(0x2344), ~0x00ffff00, 0xff00000c); in cpt_pm_init()
293 clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20); in cpt_pm_init()
310 clrsetbits_le32(RCB_REG(0x3314), 0x1f, 0xf); in ppt_pm_init()
326 clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060); in ppt_pm_init()
330 clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001); in ppt_pm_init()
336 clrsetbits_le32(RCB_REG(0x2344), 0xff0000ff, 0xff00000c); in ppt_pm_init()
337 clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20); in ppt_pm_init()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-omap2/omap5/
H A Ddra7xx_iodelay.c22 clrsetbits_le32((*ctrl)->control_pbias, SDCARD_PWRDNZ, in isolate_io()
24 clrsetbits_le32((*ctrl)->control_pbias, SDCARD_BIAS_PWRDNZ, in isolate_io()
29 clrsetbits_le32((*prcm)->prm_io_pmctrl, PMCTRL_ISOCLK_OVERRIDE_MASK, in isolate_io()
36 clrsetbits_le32((*ctrl)->ctrl_core_sma_sw_0, CTRL_ISOLATE_MASK, in isolate_io()
42 clrsetbits_le32((*prcm)->prm_io_pmctrl, PMCTRL_ISOCLK_OVERRIDE_MASK, in isolate_io()
63 clrsetbits_le32(base + CFG_REG_0_OFFSET, CFG_REG_CALIB_STRT_MASK, in calibrate_iodelay()
75 clrsetbits_le32(base + CFG_REG_0_OFFSET, CFG_REG_ROM_READ_MASK, in update_delay_mechanism()
/OK3568_Linux_fs/u-boot/board/sunxi/
H A Dahci.c26 clrsetbits_le32(reg_base + AHCI_PHYCS0R, in sunxi_ahci_phy_init()
29 clrsetbits_le32(reg_base + AHCI_PHYCS1R, in sunxi_ahci_phy_init()
34 clrsetbits_le32(reg_base + AHCI_PHYCS0R, (0x7 << 20), (0x3 << 20)); in sunxi_ahci_phy_init()
35 clrsetbits_le32(reg_base + AHCI_PHYCS2R, (0x1f << 5), (0x19 << 5)); in sunxi_ahci_phy_init()
/OK3568_Linux_fs/u-boot/arch/arm/mach-omap2/
H A Dclocks-common.c105 clrsetbits_le32(&dpll_regs->cm_clkmode_dpll, in do_bypass_dpll()
125 clrsetbits_le32(&dpll_regs->cm_clkmode_dpll, in do_lock_dpll()
365 clrsetbits_le32((*prcm)->cm_clksel_dpll_usb, in setup_usb_dpll()
664 clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK, in enable_clock_domain()
671 clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK, in disable_clock_domain()
699 clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK, in enable_clock_module()
726 clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK, in disable_clock_module()
793 clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, in setup_clocks_for_console()
798 clrsetbits_le32((*prcm)->cm_l4per_uart1_clkctrl, in setup_clocks_for_console()
803 clrsetbits_le32((*prcm)->cm_l4per_uart2_clkctrl, in setup_clocks_for_console()
[all …]
/OK3568_Linux_fs/u-boot/drivers/gpio/
H A Dstm32_gpio.c63 clrsetbits_le32(&gpio_regs->afr[dsc->pin >> 3], 0xF << i, ctl->af << i); in stm32_gpio_config()
67 clrsetbits_le32(&gpio_regs->moder, 0x3 << i, ctl->mode << i); in stm32_gpio_config()
68 clrsetbits_le32(&gpio_regs->otyper, 0x3 << i, ctl->otype << i); in stm32_gpio_config()
69 clrsetbits_le32(&gpio_regs->ospeedr, 0x3 << i, ctl->speed << i); in stm32_gpio_config()
70 clrsetbits_le32(&gpio_regs->pupdr, 0x3 << i, ctl->pupd << i); in stm32_gpio_config()
H A Dstm32f7_gpio.c34 clrsetbits_le32(&regs->moder, mask, STM32_GPIO_MODE_IN << bits_index); in stm32_gpio_direction_input()
47 clrsetbits_le32(&regs->moder, mask, STM32_GPIO_MODE_OUT << bits_index); in stm32_gpio_direction_output()
49 clrsetbits_le32(&regs->odr, mask, value ? mask : 0); in stm32_gpio_direction_output()
68 clrsetbits_le32(&regs->odr, mask, value ? mask : 0); in stm32_gpio_set_value()
/OK3568_Linux_fs/u-boot/arch/arm/mach-exynos/
H A Dclock.c865 clrsetbits_le32(addr, clear_bit, set_bit); in exynos4_set_mmc_clk()
888 clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8), in exynos5_set_mmc_clk()
909 clrsetbits_le32(addr, 0x3ff << shift, (div & 0x3ff) << shift); in exynos5420_set_mmc_clk()
1089 clrsetbits_le32(&clk->src_lcd0, 0xf, 0x6); in exynos4_set_lcd_clk()
1113 clrsetbits_le32(&clk->div_lcd0, 0xf, 0x1); in exynos4_set_lcd_clk()
1141 clrsetbits_le32(&clk->src_disp1_0, 0xf, 0x6); in exynos5_set_lcd_clk()
1165 clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0); in exynos5_set_lcd_clk()
1214 clrsetbits_le32(&clk->div_disp10, 0xf << 0, 0x0 << 0); in exynos5800_set_lcd_clk()
1230 clrsetbits_le32(&clk->src_lcd0, 0xf << 12, 0x6 << 12); in exynos4_set_mipi_clk()
1264 clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16); in exynos4_set_mipi_clk()
[all …]
/OK3568_Linux_fs/u-boot/drivers/pinctrl/
H A Dpinctrl_stm32.c29 clrsetbits_le32(&regs->afr[desc->offset >> 3], AFR_MASK << index, in stm32_gpio_config()
33 clrsetbits_le32(&regs->moder, MODE_BITS_MASK << index, in stm32_gpio_config()
35 clrsetbits_le32(&regs->ospeedr, OSPEED_MASK << index, in stm32_gpio_config()
37 clrsetbits_le32(&regs->pupdr, PUPD_MASK << index, ctl->pupd << index); in stm32_gpio_config()
40 clrsetbits_le32(&regs->otyper, OTYPE_MSK << index, ctl->otype << index); in stm32_gpio_config()
/OK3568_Linux_fs/u-boot/drivers/video/rockchip/
H A Drk_vop.c56 clrsetbits_le32(&regs->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR, in rkvop_enable()
84 clrsetbits_le32(&regs->win0_ctrl0, in rkvop_enable()
113 clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN, in rkvop_enable_output()
118 clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN, in rkvop_enable_output()
123 clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN, in rkvop_enable_output()
128 clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN, in rkvop_enable_output()
171 clrsetbits_le32(&regs->dsp_ctrl0, M_DSP_OUT_MODE, in rkvop_mode_set()

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