865 	clrsetbits_le32(addr, clear_bit, set_bit);  in exynos4_set_mmc_clk()
888 	clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),  in exynos5_set_mmc_clk()
909 	clrsetbits_le32(addr, 0x3ff << shift, (div & 0x3ff) << shift);  in exynos5420_set_mmc_clk()
1089 	clrsetbits_le32(&clk->src_lcd0, 0xf, 0x6);  in exynos4_set_lcd_clk()
1113 	clrsetbits_le32(&clk->div_lcd0, 0xf, 0x1);  in exynos4_set_lcd_clk()
1141 	clrsetbits_le32(&clk->src_disp1_0, 0xf, 0x6);  in exynos5_set_lcd_clk()
1165 	clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0);  in exynos5_set_lcd_clk()
1214 	clrsetbits_le32(&clk->div_disp10, 0xf << 0, 0x0 << 0);  in exynos5800_set_lcd_clk()
1230 	clrsetbits_le32(&clk->src_lcd0, 0xf << 12, 0x6 << 12);  in exynos4_set_mipi_clk()
1264 	clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16);  in exynos4_set_mipi_clk()
1329 		clrsetbits_le32(&clk->src_mau, AUDIO0_SEL_MASK,  in exynos5_set_i2s_clk_source()
1333 		clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK,  in exynos5_set_i2s_clk_source()
1363 		clrsetbits_le32(&clk->div_mau, AUDIO_0_RATIO_MASK,  in exynos5_set_i2s_clk_prescaler()
1372 		clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK,  in exynos5_set_i2s_clk_prescaler()
1490 	clrsetbits_le32(reg, mask << shift, (main & mask) << shift);  in exynos5_set_spi_clk()
1491 	clrsetbits_le32(reg, mask << pre_shift, (fine & mask) << pre_shift);  in exynos5_set_spi_clk()
1554 	clrsetbits_le32(reg, div_mask << shift, (main & div_mask) << shift);  in exynos5420_set_spi_clk()
1555 	clrsetbits_le32(pre_reg, pre_div_mask << pre_shift,  in exynos5420_set_spi_clk()